Efficient adaptation of the Karatsuba algorithm for implementing on FPGA very large scale multipliers for cryptographic algorithms

Received Jul 11, 2020 Revised Sep 28, 2020 Accepted Oct 8, 2020 Here, we present a modified version of the Karatsuba algorithm to facilitate the FPGA-based implementation of three signed multipliers: 32-bit × 32-bit, 128-bit x 128-bit, and 512-bit × 512-bit. We also implement the conventional 32-bit × 32-bit multiplier for comparative purposes. The Karatsuba algorithm is preferable for multiplications with very large operands such as 64-bit × 64bit, 128-bit × 128-bit, 256-bit × 256-bit, 512-bit × 512-bit multipliers and up. Experimental results show that the Karatsuba multiplier uses less hardware in the FPGA compared to the conventional multiplier. The Xilinx xc7k325tfbg900 FPGA using the Genesis 2 development board is used to implement the proposed scheme. The results obtained are promising for applications that require rapid implementation and reconfiguration of cryptographic algorithms.


INTRODUCTION
The need to protect data and information is crucial; it can make the difference between life and death. More particularly, in the military field, winning a war relies heavily on the protection of information [1]. The use of encryption keys is one of the means used to preserve the authenticity, confidentiality, nondenial, and integrity of the data. Encrypted messages use cryptographic keys, which are a binary number ranging from 0 to n. Figure 1 below shows an example of a block diagram to encrypt a message. The longer the cryptographic key, the more robust its decryption. The length of the key depends on the type of information protection desired to achieve. Therefore, the nature of the mission and the operation heavily influence the length of a key. And finally, it depends on the severity of the damage that could occur if the information is intercepted and decrypted. Most of the cryptographic algorithms are very difficult to decipher; the theoretical foundations are substantial [2]. As with any encryption algorithm, we perform a lot of arithmetical operations, and we need to find methods to accelerate these basic arithmetic operations. These methods are geared towards the multiplication of large numbers. Keys are ranging in length from 64 bits to 4096 bits depending on the security level we want to achieve and the type of the key generator used to generate them. As we said before, the longer the cryptographic keys, the stronger the cryptographic algorithm will be. For instance, we have the algorithms AES-128, DH, DSA, RSA-3072, SHA-256, and ECDH, ECDSA-256 present a security level of 128 bis. The algorithms AES-192, SHA-384, ECDH, ECDSA-384 provide a security level of 192 bits, and finally, the algorithms AES-256, SHA-512, ECDH, and ECDSA-521 exhibit a security level of 256 bits [3].
Harika et al. have presented a critical review of four multiplication algorithms, which are shift-And-Add Multiplier, Carry Save Adder, Booth Multiplier, and a modified version of the Booth multiplier. Based on this article, the Carry Save Adder was found to be more efficient in terms of execution time and less space in the FPGA than the other multiplication algorithms mentioned above. Different multiplication algorithms exist, such as Grid, Wallace-tree, Vedic, Lattice, Combinational, Sequential, Array and Montgomery, and Karatsuba [4,5]. Several articles proposed implementation methods on FPGA of the Karatsuba algorithm. Yang has introduced a scheme for implementing a 256-bit x 256-bit multiplier, which exhibits 50% efficiency compared to traditional implementations [6].
In this article, a new scheme for implementing the Karatsuba multiplier. The Karatsuba multiplier is very efficient in multiplying very large numbers, which constitutes an excellent asset in achieving complex cryptographic processors [7][8][9]. The conventional multiplication method has a complexity O(N 2 ), while Karatsuba has a complexity of O(N log3/log2 ). The following section will present the theoretical foundations for the Karatsuba algorithm and used the finding to implement a third-degree Karatsuba multiplier. Section 3 will introduce the proposed scheme; section 4 will show the experimental results.

THIRD-DEGREE KARATSUBA ANALYSIS
Here, we present the theoretical foundation for developing a third-degree Karatsuba multiplier formula. We will be using it to implement 32-bit × 32-bit Karatsuba multiplier, 128-bit × 128-bit Karatsuba multiplier, and 512-bit × 512-bit Karatsuba multiplier into FPGA. Weimerskirch laid out a more in-depth examination of the Karatsuba algorithm [10]. Let A(x) and B(x) the two operands of the third-degree Karatsuba multipliers.

Simulation results
For the sake of visibility, we present a shortened part of the simulations in Figure 4, Figure 5, and Figure 6. The results for the three implemented multipliers are consistent and give the expected values.

Implementation results
As shown in Figure 7, the implementation on FPGA of the 32-bit × 32-bit does not display any error. Of the 500 limited IO capability, only 64 are bounded, and 1844/203800 slice LUTs are used. Regarding 128-bit x 128-bit. By quadrupling the multiplier size, we multiply by a factor of 10 the size of the slice LUTs used, as depicted in Figure 8. The implementation of the 128-bit x 128-bit multiplier exceeded the IO capabilities of the FPGA, as shown in Figure 8. And it got worse with the implementation of the 512-bit x 512-bit multiplier, as shown in Figure 9. This result is not a surprise and does not depends on the scheme but rather the capacity of the FPGA used.

CONCLUSION
In this paper, we have proposed a modified version of the Karatsuba algorithm as well as a new scheme to facilitate FPGA implementation. Results obtained from 32-bit x 32-bit Karatsuba multiplier, 128bit x 128-bit Karatsuba multiplier, and 512-bit x 512-bit Karatsuba multiplier have met the expectation. They are promising for applications that require the rapid implementation and reconfiguration of cryptographic algorithms. The next step is to use these multipliers to implement a complete cryptographic algorithm on FPGA.