Characterization and hierarchical static timing analysis of mixed-signal design

Received Jun 2, 2020 Revised Oct 1, 2020 Accepted Jan 10, 2021 As the technology grows, the tendency to increase the data rate also increases. Clocks with higher frequencies have to be generated to meet the increased data rate. Any mismatch between the clock rate and data rate will lead to the capture of the wrong data. Hence performing timing analysis for any design to validate the capture of correct data plays a major role in any System on chip. This paper explains the procedure followed to perform timing analysis for any mixed-signal design.


INTRODUCTION
The Static Timing Analysis (STA) is one of the techniques available to verify the timing of any design. An alternative approach that is also available to verify the timing is the timing simulation which can verify the functionality along with timing verification of any design.
STA is said to be static since the analysis of any design is statically performed and does not rely upon the data values which are being applied at the input pins. This contrasts with simulation-based timing analysis where different patterns of stimulus signal are applied at the input and then the resulting behavior for all patterns is observed and verified. Given a design with the definition of the external environment and a set of input clock definitions, the purpose of static timing analysis is to verify and validate if the design is capable to operate at the rated speed.
The design under analysis is defined using a hardware description language such as Verilog or VHDL. The external environment along with the clock definitions are defined using design constraints (SDC) or an equivalent format. The timing reports are in ASCII form with multiple columns. Each column shows one attribute of the path delay [1,2].
The design performance and its functionality can be limited by the noise in mixed-signal designs. The noise occurs due to many reasons like noise on primary inputs or power supplies or due to crosstalk with other signals. The noise can limit the operating frequency of the design and can also cause functional failures. Thus, a design implemented must be verified to be robust which means that it should have the capability to withstand noise without affecting the design performance. Verification based upon logic simulation cannot handle the effects of noise, on-chip variations, and crosstalk.

ON-CHIP VARIATION
Different portions on a chip have different PVT conditions because of the variations in environmental and process parameters. These variations lead to violation in timing; changes in MOS characterization can affect wire and cell delays. To account for these PVT variations, OCV analysis must be done during STA. Since data and clock paths may be affected differently by on-chip variation, timing verification can model this variation effect by making PVT conditions for capture and launch paths to be different. In STA these variations can be modeled by derating the delays of paths either making it faster or slower as per the requirement. Net and cell delay can be derated while modeling OCV [3][4][5].

Derating OCV for setup check
The worst condition possible for setup violation due to OCV occurs when launching clock path and data path OCV leads to the longest delay while the capturing clock path has OCV conditions which lead to the shortest delay [6][7][8]. This condition is the most restrictive case for setup check which is also shown in Figure 1. To account for these violations, the following constraints are provided which will derate early/minimum paths by -10% i.e the path is made more faster and will derate late/maximum-paths by +10% i.e., the path is delayed more. set-timing-derate -early 0.9 set -timing-derate -late 1.1.
To avoid setup violation the data path has to be multiplied with late derate (delayed more) and capture path should be multiplied with early derate (made faster). Net and cell delays can also be derated using -net-delay and -cell-delay with set-timing-derate.

Derating OCV for hold check
The worst condition possible for hold violation due to OCV occurs when launching clock path and data path OCV leads to the shortest delay while the capturing clock path has OCV conditions which lead to the longest delay. This condition is the most restrictive case for hold check which is also shown in Figure 2. To account for these violations, the following constraints are provided which will derate early/minimum paths by -10% i.e., the path is made more faster and will derate late/maximum-paths by +10% i.e the path is delayed more. set-timing-derate -early 0.9 set -timing-derate -late 1.1. To avoid hold violation the data path has to be multiplied with early derate (made faster) and capture path should be multiplied with late derate (delayed more).

Advanced on-chip variation
The concept of OCV modeling was based on fixed derating factor. This is a kind of pessimism. This can't be applied all the time. To overcome this the concept of Advanced On-Chip Variation (AOCV) is used. In AOCV, the derating factor isn't fixed whereas it is based on the depth and location of logic. AOCV differs from OCV where different derate values can be given for the cells. a) Distance-based AOCV: This is used in modeling global variation effects. Different parts will have different variations. So as the distance increases variations also increases according to which derate value is decided. b) Depth based AOCV: This is used in modeling local variation effects. These variations cancel out as the distance increases. So as depth increases the derate value decreases [10].

PARASITIC CORNERS
In Timing analysis has to be performed at various corners thus parasitic extraction is done at different corners. Interconnect wires in any design form two important devices in any circuit which are resistors and capacitors. This is because all the interconnect wires are modeled very nearer to each other [11].

Capacitance of interconnect wire
One of the devices formed by interconnect wire is a capacitor. Capacitance is dependent on various parameters such as Dielectric constant, Width of Metal (W), Thickness of Metal (T) Spacing between the metals (S) and Thickness of Dielectric (H) As the technology value decreases these parameters also decreases and the capacitance varies based on that [12].

Resistance of interconnect wire
All materials are associated with resistivity. Conductors have lower resistivity compared to semiconductors and insulators. Resistivity varies based on Temperature and the type of material. Resistance per unit length is given by ρ/ [(Thickness of metal) *(Width of metal)]. For a material at a particular temperature as the technology decreases the parameters such as width and thickness decrease and hence resistance increases which is not desired. Because circuit delay is directly proportional to resistance and if the delay value is high then it's impossible to design a high-speed circuit [13][14][15][16].
Hence to reduce resistance, resistivity can be made low by using different materials with lesser resistivity value. Interconnect parameters also depend on the number of drivers connected and the length of interconnect wire. High fanout indicates that the driver can drive more load and hence driver resistance is less (more current to drive more load) whereas low fanout indicates that the driver resistance is high. There may be 4 cases based on interconnect length and fanout of the driver as given in Table 1. Among the above cases only 2 nd and 3 rd cases are important, because in the 1 st case resources are not utilized properly and in the 4 the circuit doesn't work properly. The driver lacks in its driving capability till the end of the nets. Let Rd and Rw be the driver and wire resistance. In the 2 nd case, Rd is greater than Rw whereas in 3 rd case Rw is greater than Rd. Hence in 2 nd case Driver resistance is dominant and in 3 rd Interconnect resistance is dominant. Driver resistance dominated paths mean Interconnect resistance is less which also means Interconnect capacitance is large. In terms of capacitance it is Interconnect capacitance dominated paths and the other is Interconnect resistance dominated path. Based on these there are two corners defined which are: C-best known as Cmin (minimum C, maximum R) and C-worst known as Cmax (maximum C, minimum R). There are other corners too which are RCbest, RCworst and typical.  [17][18][19][20]. b) Cworst: This corner refers to those which has maximum capacitance. Hence known as Cmax corner.
Interconnect resistance is smaller compared to the Typical corner. This corner results in the largest paths with short nets and is used for max path analysis. c) RCbest: This corner refers to those which minimize interconnect RC product hence known as RCmin corner. This corner has the shortest path delay for paths with long interconnects and is used for min path analysis. d) RCworst: This corner refers to those which maximize the interconnect RC product. Hence also known as RCmax corner. This corner has the highest path delay value for paths with long interconnects and is used for max path analysis. e) Typical: This corner refers to the nominal value of interconnect capacitance and resistance. Timing analysis is performed at each different corner and violations are observed and corrected accordingly.

HSTA FLOW
Static Timing Analysis of any mixed-signal design is carried out using HSTA flow which is shown in Figure 3. The design is partitioned hierarchically and decision on which cells should undergo .lib and QTM generation is made. Parasitic are also extracted at few corners. With all of the above data along with the netlists of top-level cell and the cells for which parasitic are extracted, static Timing analysis is performed using either Synopsys Prime Time or Nano time [21][22][23].

Generation of .libs
Characterization of lower-level cells is done using SiliconSmart. The generated .libs has all the required timing information. .LIBS generated for one of the cell cDqOmux. The cell is characterized at one of the corners and the various parameters can be observed. The .lib contains a description of each pin and power supplies used.

Generation of QTM libs
Lib extraction for analog cells follows a separate procedure. Characterization of such cells is done using the Quick Timing Model. PrimeTime helps in generating QTM libs for Analog blocks. The QTM libs generated for analog block is as shown in Listing. 3. for one of the cells cZQCal. QTMs are considered as dummy .libs as they do not have any timing information. They only contain the direction of each pin of a cell with capacitance at each pin as shown in Listing 1. With all the .libs and QTM libs generated for lower-level cells in prior, timing analysis at the top level takes less time. All the netlists, parasitics and .libs are provided as inputs for either PrimeTime or Nano time to carry timing analysis [24,25].

Analysis coverage
Analysis coverage of any design on performing timing analysis looks like as shown in Listing 2.

Listing 2. Analysis coverage report
It can be observed that 2% of the paths are violated due to setup check and 3% of the paths are violated due to hold check and similarly 4% of the paths are untested due to setup and hold check. All these violations should be corrected in-order to capture correct data.

CONCLUSION
Hierarchical Static Timing Analysis flow has helped in analyzing violations at each lower level and has helped in a great reduction of analysis time. The division of entire design to different levels and parasitic extraction separately for such levels skipping QTM and .lib cells for which timing information is already available reduces the execution time to a great extent. From the timing reports obtained, the violation paths can be easily identified which will usually be a register to register path. The slack value indicates the difference between the data arrival time and the time which was expected for the data to reach the input of the register. This value indicates the extent of the violation and will be usually in nanoseconds. Based on whether it is setup violation or hold violation buffer cells whose cell delay corresponds to the slack value is added either in the data path or in a clock path. From this the data is exactly sampled at either rising or falling edge of clock based on the type of edge triggering. All the data is properly written or read from the memory without any loss of data. Thus, timing analysis plays a key role in any VLSI design.