Effect of integrated power and clock networks on combinational circuits

Received Jun 28, 2020 Revised Aug 25, 2020 Accepted Oct 8, 2020 Reduction of power consumption is necessary in a system on chip. To achieve this, power and clock networks can be integrated. This leads to a significant reduction in power consumption in a circuit. This paper explores the effect of such a network on various combinational circuits and compares the power consumption of these circuits with conventional combinational circuits. The combinational circuits which are powered by the proposed circuit consume lesser power as compared to conventional combinational circuits.


INTRODUCTION
As integrated circuits become more complex, the power consumption increases and the performance also increases. The continuous scaling of transistors and the increase in their frequency of operation has led to an increase in the overall power consumption of the chip. This increase in the complexity of the chip, in accordance with the Moore's Law, has also led to increased power densities within the Integrated circuit. A primary consumer of power on-chip is the Clock Distribution Network or the Clock Tree. Traditionally, it wa consumes anywhere between 30% to 50 % of the total dynamic power [1][2][3][4][5].
Complex integrated circuits have higher performance and lower power utilisation. With limited onchip resources circuit designing becomes a complex task. These resources are majorly used by the three main lines of clock, ground and power in a IC. Characteristics of a circuit differ from one another and the net result is heavy utilisation of existing on-chip resources [6][7][8].
With limited on-chip resources it becomes necessary to design circuits which reduce the power consumption. One such circuit is an integrated power and clock distribution circuit which reduces power consumption significantly by around 60% The effectiveness of this designed circuit has been tested on various combinational circuits [9][10][11][12][13][14][15].
The research articles which have been published on GIPAC [1] include various methods for decreasing energy usage in circuits. Earlier literature had tried merging power and clock signals throughout the chip. The combined signals were filtered and two signals were obtained from the GIPAC [1] network.

243
Higher frequency signal is the clock signal and the signal with a constant dc value is Vcc or the power signal. Hence filtering the signals into two separate components is plausible. Another literary work explores the possibility of eliminaing the whole CDN [2], totally by merging the two networks. Newer literature on combinatorial wire-wireless clock distribution networks [3] suggests a combined circuit consisting of wired and wireless clock networks. Here circuits were designed using transmitters and receivers, and generated a clock signal which was wireless in nature. The circuit used On-Off-Keying (OOK) transceivers [3] which were used for reduction in propagation delay , increase power eficiency and reduce the complexity of the circuit. This circuit had a propogation delay lower than a normal clock circuit. The circuit also had a reduced clock skew [16][17][18][19][20][21].
The research articles which have been published on GIPAC [1] include various methods for decreasing energy usage in circuits. Earlier literature had tried merging power and clock signals throughout the chip. The combined signals were filtered and two signals were obtained from the GIPAC [1] network. Higher frequency signal is the clock signal and the signal with a constant dc value is Vcc or the power signal. Hence filtering the signals into two separate components is plausible.
Another literary work explores the possibility of eliminaing the whole CDN [2], totally by merging the two networks . As the clock network consists of a clock grid driven by a global h-tree, the metal lines implemented both horizontally and vertically would require atleast four metal layers. If a similar power network is considered throughout the chip then a total of 6 metal layers would be used [22][23][24][25].
If the clock and power networks were to be merged then a total of four metal layers would be required thus saving two metal layers. Comparing typical resonant networks with these circuits, a signal generated by this circuit has a swing of 400 mV around Vdc. The usual resonant clock networks [11] generate a full swing clock signal from 0 to VDD The output of the IPCDN [2] circuit can be directly connected to the power line of the entire circuit. This helps to eliminate local clock networks [9] and also the use of filter circuits.. Also, the voltage swing of 400mV for the generated signa it is quite low as compared to the traditional clock networks. But in a IPCDN [2] circuit needs a clock buffer to convert the generated signal into a full swing clock signal, which is necessary to operate the sequential circuits.
Newer literature on combinatorial wire-wireless clock distribution networks [3] suggests a combined circuit consisting of wired and wireless clock networks. Here circuits were designed using transmitters and receivers, and generated a clock signal which was wireless in nature. The circuit used On-Off-Keying (OOK) transceivers [3] which were used for reduction in propagation delay , increase power eficiency and reduce the complexity of the circuit. This circuit had a propogation delay lower than a normal clock circuit. The circuit also had a reduced clock skew.

RESEARCH METHOD
This paper explores a CMOS oscillator circuit which generates a combined signal used to run a combinational circuits. The designed circuit was tested on a inverter. NAND and a NOR gate for its effectiveness.
The designed circuit is a transistor based CMOS oscillator circuit and when simulated, the circuit [12] generates a 415mV swing. The generated signal is the pwr_clk signal and has a dc component alongwith a sinusoidal swing . The generated signal can be directly connected to run a Inverter, NAND and a NOR gate.
The designed circuit can be used to integrate power and clock network signals and can be used to drive the digital part of a chip, as analog part of the circuit is vulnerable to fluctuations in the power supply. The proposed circuit is as shown in Figure 1. The signals generated are of opposing polarity to each other.
The generated pwr_clk signal can be connected directly to run a Inverter, NAND and NOR gate, but to connect to a sequential circuit, a full swing clock signal is necessary and this calls for a clock buffer circuit.

RESULTS AND DISCUSSION
To simulate the designed circuit , SPICE CIS lite version 17.2 was used. The simulation results show the circuit of a CMOS oscillator implemented on a NAND gate as shown in Figure 2. The CMOS oscillator implementation on a inverter circuit is shown in Figure 3. Figure 4 shows the implementation of a CMOS oscillator circuit on a NOR gate. Figure 5 shows the simulation output for a NAND gate. The Voltage transfer characteristics of a inverter implemented with a CMOS oscillator is shown in Figure 6. Simulation output of a Inverter with a CMOS oscillator is shown in Figure 7. Figure 8 shows the simulation output of a NOR gate.   Table 1 shows the comparison of Voltage swing for GIPAC, IPCDN circuit and the designed CMOS oscillator circuit. Table 2 shows the comparison for power dissipation and transistor count for IPCDN and designed CMOS oscillator circuit. Table 3 shows comparison of power consumption for inverter with CMOS oscillator circuit and a typical inverter circuit. Table 4 shows comparison of power consumption in NAND gate with CMOS oscillator and a normal NAND gate. Table 5 shows comparison of power consumption in NOR gate with and without the CMOS oscillator circuit.

CONCLUSION
In this paper, the proposed circuit have successfully designed to generate a combined signal. Results of simulation show signals upto 5 GHz an be generated. Implemented circuit has been tested on combinational circuits like Inverter, NAND and NOR gate and it is found that these gates consume 10 times lesser power with the proposed circuit as compared to conventional NAND , NOR and NOT gates.