Surface potential modeling of dual metal gate-graded channel- dual oxide thickness with two dielectric constant different of surrounding gate MOSFET

Received Apr 9, 2019 Revised Oct 25, 2019 Accepted Nov 11, 2019 An Analytical study for the surface potential, threshold voltage and Subthreshold swing (SS) of Dual-metal Gate Graded channel and Dual Oxide Thickness with two dielectric constant different cylindrical gate surroundinggate (DMG-GC-DOTTDCD) metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed to investigate short-channel effects (SCEs). The performance of the modified structure was studied by developing physics-based analytical models for the surface potential, threshold voltage shift, and Subthreshold swing. It is shown that the novel MOSFET could significantly reduce threshold voltage shift and Subthreshold swing, can also provides improved electron transport and reduced short channel effects (SCE). Results reveal that the DMG-GC-DOTTDCD devices with different dielectric constant offer superior characteristics as compared to DMG-GC-DOT devices. The derived analytical models agree well with simulation by ATLAS.


INTRODUCTION
The decrease of the dimensions in transistors MOSFETS is not the fruit of the hazard and follows a law of reduction of generalized scale [1]. This law is in fact a version improved by the first law drafted by Dennard In 1974. The principle of these laws is to quantify the major parameters of a technology (dimensions, doping, capacity, current...) using a single factor K in order to easily predict the expected performance for the future nodes technological [2].
This reduction in size leads in the other hand to the proliferation of parasitic effects. Let us quote for example the effects of short channel (decrease of the threshold voltage of the transistor, DIBL ...) [3], the leakage current gate, and the technological fluctuations (inhomogeneities of doping, thickness ...). These effects come to disrupt in a significant way the functioning of the integrated circuit.
So, it becomes important to develop new architectures of component and / or use other materials than those traditionally used in microelectronics (Si, SiO2, silicon polycristrallin ...) while deviating the least possible from the currently maitrized manufacturing processes. Several types of devices are at present for the study in applied research and in research and at the large founders of integrated circuits. Examples include the devices with silicon on isolant (SOI), the transistors multigrilles (DG for Double Gate, GAA for All Around, SG Surrounding Gate ...). These new architectures must offer the advantage of better control of potential in the channel by the gate voltage what will make it possible to still push back the limits of the miniaturization of the MOSFETS. The structure Gate-All-Around MOSFET also called "surroundinggate MOSFET" [4], offers a better control of the electrostatic potential by appearing with DG MOSFET structure [5].
In recent years, to reduce the SCEs and improve hot carrier reliability, various studies have been carried out on SG MOSFET. Many works suggested that gate material engineering as the solution to overcome these effects, Dual-material gate (DMG) structure using two metals with different work functions which improves SCEs than single Material (SM) SG MOSFET [6]. Many authors have reported the channel engineering, graded channel (GC) [7], as one of the possible solution for suppressing the SCEs and enhancing the device performance. The use of GC, with two doping region highly doped region near source end and low doped region near drain end , showed significant improvement of hot carrier reliability and immunity against SCEs. Many works have also reported high-k dielectrics as an alternative to replace SiO2 as the gate dielectric In order to reduce gate leakage current and improve gate controllability over the channel [8,9]. Therefore in this research work, we have developed the model considering all important device engineering, as Dual-metal Gate Graded channel and Dual Oxide Thickness with different dielectric constant surrounding-gate (DMG-GC-DOT), using parabolic approximation method which is valid for the other structures shown in the Figure1(a) [10]. An intensive comparative study of other device structure is also carried out. Also the analytical model results are verified by comparing them with results obtained from the simulation using ATLAS.

MODEL DERIVATION
A cross section along the channel direction of the DMG-GC-DOTTDCD MOSFET is shown in Figure 1 Analytical and numerical models of threshold voltage and subthreshold swing for DMG-GC-DOTTDCD MOSFET are compared to those for DMG-GC-DOT MOSFET.

Surface potential model
The electrostatic potential and electric field distribution in the silicon channel can be derived by solving Poisson's equation. Neglecting the influence of charge carriers and fixed charges, the Poisson's equation in cylindrical coordinates in two regions (i=1, 2) can be written as: The potential distribution in the two regions is assumed to be a parabolic profile [11] in the radial direction and can be written as: The electric field in the centre of the silicon pillar is zero by symmetry The electric flux at the oxide-silicon interface is continuous  are the dielectric constant of high-k and SiO2 gate oxide respectively, and 1 ox t is the oxide layer of region 1 L and 2 ox t is oxide layer of region FBi V is the flat band voltages of the two regions will be different and they are given as follows: Using boundary conditions, the coefficients i A and i B (i = 1, 2) can be determined as: By differentiating the surface potential   , si r R z   with respect to z, the electric field E (z) at the channel surface in the z direction is given as:

Threshold voltage model
In a DMG-GC-DOTTDCD MOSFET structure, the position of the minimum surface potential is always located under the gate material having higher work function ( 1 M ). Therefore, the position of

RESULTS AND DISCUSSION
In this section, it is explained the results of research and at the same time is given the comprehensive discussion. Results can be presented in figures, graphs, tables and others that make the reader understand easily [2], [5]. The discussion can be made in several sub-chapters. Now the performance of DMG-GC-DOTTDCD in threshold voltage shift, SS and DIBL will be examined. The performance of DMG-GC-DOTTDCD with different dielectric oxide constant, which Silicon dioxide (SiO2) is taken as low-k gate oxide material and hafnium dioxide (HfO2) is taken as high-k gate oxide material with permittivity

CONCLUSION
By solving 2D Poisson's equation in the two channel regions, an analytical model comprising surface potential, threshold voltage shift and DIBL for a DMG-GC-DOTTDCD MOSFET has been developed in order to improve short channel effects and hot carrier effects. Using this analytical model, the characteristics of DMG-GC-DOTTDCD are investigated in terms of surface potential, threshold voltage shift, and DIBL. It has been demonstrated that DMG-GC-DOTTDCD MOSFET provides a better immunity to SCEs as compared to DMG-GC-DOT MOSFET. It is evident from the results that the properoptimization of dual oxide thickness with different dielectric constant in DMG-GC-DOTTDCD MOSFET significantly reduces DIBL effect and subthreshold swing. The results obtained from the models agree well with the results obtained using simulation ATLAS.