Low power 11T adder comparator design

Received Apr 15, 2019 Revised Oct 10, 2019 Accepted Nov 11, 2019 Comparator is a basic arithmetic component in a digital system and adders are the basic block of processor unit, the performance of adder will improve the system performance. The proposed 11T adder comparator is consists of three main components, namely XOR, inverter, and MUX logic. The circuit is designed and implemented based on top-down approach with 11 transistors. The proposed cell can be used at higher temperature with minimal power loss. It also gives faster response for the carry output. The proposed comparator circuit shows 63.80% improvement in power consumption than other circuits.


INTRODUCTION
The comparator is one of the vital components of digital systems. The CMOS comparators are designed with different power dissipation, delay and circuit complexity. The implementation of full adder in comparator has been constantly improving since it first design. The adder as a design, mainly to reduce the number of transistors, minimize the power consumption and increase the speed. It has been used in many electronic devices and wireless sensor networks (WSN). Most of the researchers have designed the comparator circuit and improved the performance in aspect of sensitivity, offset, speed and power dissipation by using different type of topologies and circuit methods [1][2].
Magnitude comparator is used in digital system to compare two inputs (A and B) and relative magnitude to find three states of outcome whether A is less than B, A is equal to B or A is greater than B. The main focus is to use full adder for low magnitude comparator. The magnitude comparator with full adder inputs (A and B), inverts the input A and AND gates result as output. The three outputs are obtained by different combination of inputs. CMOS Comparator is designed with various logic styles into an integrated design methodology. A CMOS Comparator design, both quantitative and qualitative has been individually investigated and analyzed. Clocked regeneration comparators are called as dynamic comparators. Normally, these comparators are used in many applications with Analog to Digital Converters and need quick decision and positive feedback in the regeneration circuits. Many designs are analyzed in in terms of noise, offset, random decision errors, speed and kick-back noise [3][4][5][6][7]. Due to the disadvantages of dynamic comparator, a study of double-tail comparator is been proposed [8]. The comparator operates at lower supply voltages due to less stacking effect. It is also suitable for quick latching and independent of the input common mode voltage as well as a small current in the input stage for low offset. Generally, the three major concerns of

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CMOS comparator design are power consumption, speed and chip area. Hence these estimates create conflict with others. Each individual concern cannot be optimized independently [9]. The GDI and PTL logics were used for One bit hybrid comparator consisting of 17T (8 PMOS and 9 NMOS). The basic building block (9T Full adder) is implemented in PTL and GDI logic. The hybrid logic used results in additional propagation delay along with switching penalty. Moreover, the increased complexity and overall performance degradation are caused. This paper is arranged as follows. The section 2 explains the proposed design with layout and generated waveforms. Section 3 includes the results analysis and discussion. The paper ends with conclusion and references.

PROPOSED DESIGN
The proposed comparator design has an adder circuit with 11 transistors as shown in Figure 1 and Figure 2. Due to minimum number of transistors, the comparator circuit consumes less power. It consists of three main components, namely XOR, inverter, and MUX logic. The (one bit) output Boolean expression for SUM and CARRY of adder are shown below: The three comparative outputs are obtained by connecting the inputs A and B to the full adder and the input C is grounded. When A>B, the comparator output acts as the carry output (1-bit). The AND gate input combinations are used for the combinations of A=B and B>A. When B>A, the AND gate input combinations are B and Abar and for A=B, it is SUM and VDD.

RESULT AND DISCUSSION
The proposed 11T adder comparator is designed using three main components (XOR, inverter, and MUX logic), other comparator (1 bit) circuits (6T, 14T, 7T, 12T) and Shannon are simulated using Microwind CAD tool. Figure 3 shows the layout of comparator which is simulated at 65nm CMOS technology by using BSIM 4 VLSI CAD tool. The proposed 11T adder comparator circuit provides fast, minimum power and less area when compared to the four adder cell based comparator circuits. The reasons are as follows: The Shannon comparator circuit dissipates large power and more delay due to the voltage swing restoration problem in their adder component [10].
In the MUX-14T adder cell, the input node dissipates more power to transmit the voltage level [11]. Due to the input nodes transients, the MCIT-7T adder cell based circuit consumes high power [12]. The large power consumption and low speed are the main drawbacks of the MUX-12T design [13]. It is due to buffering restoration unit at AB in the carry circuit.
The proposed 11T comparator circuit is compared with 120, 90 and 45 nm feature sizes of other comparators exist in the literature. Figure 3 shows the generated layout of 11T adder comparator. The waveform of the 11T comparator is shown in Figure 4. Due to high current, minimum number of transistors, more transitions in NMOS, absence of swing restoration, and minimum critical path in comparator circuit, the proposed 11T comparator performance is improved. Table 1 shows the transient analog simulation.

Power dissipation
The power dissipation can be assign to two categories in the digital circuit design. The dynamic dissipation and also the static dissipation. Dynamic dissipation is caused due to the switching activity causes the transient current produce, when the switch is charged and discharge, the parasitic capacitance will be also affected. And for the static dissipation, it is caused by the leakage current drawn by the supply power. The static power is nothing but the product of supply voltage and leakage current. Power consumption is moderately high at 11T adder comparator cause of increase dynamic power by NMOS circuit design. Switching activity of the transistor will cause the high power consumption and it can be estimated by the vectors using the MICROWIND simulator.

Propagation delay
When the input signal of logic gate is changed, propagation delay from changes output of the logic gate occur due the load capacitance effect at output node. The 11T adder circuit is designed as high-speed circuit in latest trend.
The propagation delay of the proposed 11T adder comparator is evaluated by simulation considering increment of the capacitance as shown in Figure 5. The delay response of three different conditions, high speed (HS), high voltage (HV) and low power (LP) are described in Figure 6. The high Although the circuit is complex, the derived (1) depicts its dependency of the comparator parameters. The HS FET cells' W/L ratio is less compared to the LP FET and HV cells gives high speed.
2 ) ( / )( Td is defined as propagation delay of the comparator, W/L is the length/width ration of the transistor and Vth is threshold voltage. Due to reduced switching activity in 11T Adder based comparator, the propagation delay is minimized and it is widely used in high speed mobile communication.