A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor

Received Jul 15, 2019 Revised Sep 30, 2019 Accepted Oct 11, 2019 Power dissipation is a major issue in digital circuit design. As technology into developed into range, power and delay becomes vital nanometer parameters to ameliorate the performance of the circuit. To minimize the power consumption many low power techniques such as MTCMOS, stacking, body biasing techniques have been reported. In this paper, a new pseudo NMOS adder circuits have presented. It has designed using transmission gate and body bias technique. Simulation has been accomplished by using SPICE tool. The simulation result show the validity of the proposed techniques is reduces power dissipation from 0.367 mW to 0.267 mW and PDP reduced from 19.311pJ to 13.311pJ. Overall improvement of 29% in power consumption and 30% in PDP has obtained.


INTRODUCTION
In the present span, there is a constant advancement in VLSI technology which has caused fast decrease in size and geometries of the transistors and rise in densities of the transistor [1]. Due to this, the circuit consumes huge amount of power and many times it results to silicon failure in chips. High speed operation with low power utilization is becoming a momentous factor in the modern design of various electronics components [2]. The adder is the most critical component that's extensively used in portable devices i.e. cellular phones, remote sensors, wearable electronics and devices where very low power consumption is needed. Adder has used in the many computational power efficient circuits [3]. The body biasing is a power reduction technique used in many VLSI circuits. The equation which shows how body bias effects the threshold voltage is: Where Φ B Fermi Potential γ body effect coefficient V th0 Threshold voltage with zero V SB substrate bias V SB source to body bias voltage The leakage current is the sources of power consumption in the sub threshold circuits; this increase the threshold voltage significantly decreases the sub threshold leakage current. In order to maintain the low threshold voltage (V th ) in the static CMOS parameters, the body terminals of PMOS has connected to V DD and the NMOS body terminal connected to ground. A PMOS transistor are used as a load device and NMOS used as pseudo-NMOS logic. The merit of pseudo-NMOS logic are its high speed (large fan-in NOR gates) and low transistor count [4]. The disadvantage is the static power consumption of the pull-up transistor as well as the reduced output voltage and voltage gain, which makes the gate more liable to noise. In this paper we have proposed a schematic approach to design full adder and this adder are useful in large circuits such as multipliers. In recent year's different circuit technique have been described to improve the performance of XOR/XNOR gates, static CMOS transistor mainly contains pull-up PMOS and pull-down NMOS networks [5].
In this paper, a XOR circuit has designed using pseudo NMOS, this technique reduce power consumption and number of transistors. Adder has designed with XOR circuit and multiplexer. This proposed circuit has reduced supply voltage, less the power and small time delay reduction using sub threshold and different body biasing techniques [6]. Transmission gate have been also used in designing of carry block of proposed adder circuit. Four different circuits have been proposed in this to implement the full adder. Rest of paper organized as: Section II describes the proposed adder circuit, section III discusses simulation result about of the proposed adder, finally section VI conclude the above.

PROPOSED ADDER CIRCUIT
In circuit I, a full adder has been designed using XOR gates with the multiplexer block. XOR gate has designed using pseudo NMOS whereas multiplexer has designed using transmission gates. In circuit II, full adder has been designed using same circuit as circuit I with body biasing of PMOS substrate with V DD and NMOS substrate with V SS =GND. Supply voltage V DD had taken between 0.8 to 1.6V. Multiplexer has designed using one transmission gate; it reduced number of the transistors [7][8][9]. When the body of NMOS has biased with negative supply the channel region increase therefore rises in the threshold voltage. Full adder using XOR and MUX circuit a shown in Figure 1. Body connections in MOS devices a shown in Figure 2.  In circuit III, full adder has designed using circuits I and II with voltage V SS =-V DD or V SS <0 had taken. In it, width of transistor sized for proper output voltage swing. In Dual threshold CMOS technique, PMOS transistors are biased individually by their inputs so that each transistor have a high or low sub threshold voltage hence, low or high sub threshold leakage current, not dependent on gate's status [10]. In PMOS body biasing technique, all PMOS transistors are connected to the gate output. When PMOS network had OFF then gate output had less rise to sub threshold leakage current. When PMOS transistor is switches ON then its body had already biased low and instantaneous high leakage current has flow caused 164 the gate to switch faster and the output raise faster which has suppressed the sub threshold leakage current afterwards but only after that current has not required. In proposed technique, PMOS body biasing has done to gate output and NMOS body biasing to a voltage supply V SS (V SS <0.40V). Figure 3

a shown in (a) DTPMOS technique (b) PMOS body biasing technique (c)
The proposed technique. Shown in Adder using XOR and multiplexer (Circuit-I) a shown in. Adder using body biasing technique with NMOS substrate connected to ground (Circuit-II) a shown in Figure 5. Adder using body biasing and DTPMOS techniques (Circuit-IV) shown in Figure 7. Adder using body biasing with NMOS substrate connected to Vss (Circuit-III) a shown in Figure 6.

RESULTS AND DISCUSSION
The simulations are performed in SPICE 180nm technology with supply voltage variation from [0.8-1.6]V. Substrate biasing has been used to control the leakage current and power consumption. With help of pseudo NMOS and transmission gates number of transistors and dynamic power dissipation had reduced. It has been observed that by using proposed body bias and DTPMOS techniques more than 29% saving in power and more than 1.5% savings in delay are achieved. To evaluate the performance of the proposed body bias scheme, the implemented full adder is simulated at different supply voltages (V DD ) from 0.8V to 1.6V and the performance parameters power, delay, PDP are compared. From the comparisons made it is observed that: Also the magnitude of percentage decrease in power is more with the increase in V DD . Particularly delay of operation (V DD =0.8V) the proposed scheme incurred a penalty of 0.8% increase in delay because of less output driving capability due to the increase in threshold voltage of the device. The proposed full adder circuit has achieved more than 30% power delay product saving than the standard CMOS configuration at the different supply voltage V DD from 0.8V to 1.6V. Power dissipation and time delay with variation in VDD as shown in Table 1.

CONCLUSION
The full adder circuits using XOR and multiplexer block using body bias and DTPMOS technique have been proposed. Power and PDP is reduced to greater extent than existing method. The simulations are performed in SPICE 180nm technology. The simulation results show that the proposed adder circuit offers improved average power and average delay such as 0.267 mW and 50.601 ns. The circuit operates with more speed after applying biasing and DTPMOS technique. The proposed full adder circuit show less power consumption and PDP with reduced number of transistors. The adder designed shows minimum power dissipation of 0.267mW with PDP of 13.495 pJ at different supply voltage from V DD =0.8V to 1.6V.