Design and Implementation of a New Architecture of a Real-time Reconfigurable Digital Modulator (DM) into QPSK, 8-PSK, and 16-PSK on FPGA

ABSTRACT


INTRODUCTION
DM techniques are mostly preferred over its analog counterpart for their greater transmission capacity and greater immunity to noise [1]- [3]. Among DM techniques we distinguish the Amplitude Shift Keying (ASK), the Frequency Shift Keying (FSK) and the Phase Shift Keying (PSK). These three types of DM techniques use a sinusoid and vary its amplitude, frequency or phase to produce the ASK, the FSK or the PSK modulation respectively.
With the great advances made in the manufacturing process of integrated circuits (ICs), we are seeing an explosion in the use of digital systems in the data processing for wireless communications systems. This is due in part to the fact that digital circuits are much easier to manufacture being based on the CMOS fabrication process. Moreover, almost all transistors in CMOS digital ICs have minimum length to provide a high switching frequency. This feature ensures the design of very high frequency digital signal processors (DSP). In addition, digital ICs do not suffer from over-voltage nor from second order effects encountered in analog circuits such as noise, offset and mismatch [4]. Furthermore, with the arrival of the Field Programmable Gate Array (FPGA) technology, this phenomenon centered on digital processing techniques is accentuated even more. The advantages of the FPGA technology are based on the following five features: (1) It offers better computing power compared to digital signal processors (DSPs) benefiting from hardware parallelism, (2) enables rapid prototyping of circuits, (3) allows the reconfiguration of systems which reduces engineering costs, (4) does not use an operating system which minimizes reliability problems, and (5) unlike Applications Specific Integrated Circuits (ASICs) which requires remanufacturing in order to make an upgrade, FPGA technology allows us to achieve this by reprogramming only the necessary block or blocks in the design without respending money. As a result, the analog parts of modern communication systems have become increasingly absent. Their use is reduced to power amplification, ADC and DAC converters, and filters. Although the filters can be digital, we are still witnessing a strong use of off-chip analog components to realize the band-pass filter (BPF) found in some current communication systems. However, the FPGA technology remains the most used for data processing.
Through literature, we found several authors who chose the FPGA for their wireless communication system. For instance, Moubark et al. proposed a new architecture to realize a QPSK modulator [5]. The total power consumed by the proposed modulator is 40 mW. This result is very promising for the choice of the FPGA technology as a prototyping platform to build wireless communications systems. Over time, other architectures of the QPSK modulator have been proposed. Al Safi describes a new QPSK modulator that uses one LUT and two accumulators to generate the four phases of the QPSK [8]. Knowing that an accumulator is a register which role is to store LUT data temporarily, therefore the reading of these data will introduce delay into the phase generation process. However, the impact of this introduced delay on the system is negligible compared to the gain incurred with the reduction in the size of the circuit. In some other QPSK architectures a digitized carrier wave generator was used [6] and [7]. These subcarriers are generated from a Numerically Controlled Oscillator (NCO) to produce the I and Q modulation signals [7]. With this approach, the two multipliers, as well as the local oscillator, are no longer needed. In the quest to reduce the space occupied by the modulator in the FPGA several designs have been proposed, some of which are found in [8]- [10]. Overall, the use of the FPGA to implement digital communication systems is very well exploited in the literature [11]- [13]. This article is organized as follows. In section 1 we present the topic on the use of DM techniques in communications system design. In section 2 we will briefly review the theoretical foundations of the PSK modulation. In Section 3 a new architecture of a real-time reconfigurable PSK modulator is proposed. Sections 4 and 5 are dedicated to the presentation of simulation and experimental results respectively. In Section 6 we present an encryption key generator circuit. Finally, we conclude in Section 7.

PHASE SHIFT KEYING THEORY
In this study, the phases of developing an evaluation model of the suitability of anti-hypertensive drugs as presented in Figure 1. Development stage consists of the first Stage of making a knowledge base involving input data from the hospital, expert knowledge and knowledge derived from literature studies.
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For = 0, 1 we have: While the BPSK modulation is more robust, Quadrature Phase Shift Keying (QPSK) modulation provides higher data rate, and therefore more suited for data transmission [14]. Figure 2 shows the conventional architecture of the QPSK modulator. This circuit is fully implementable in a FPGA, and can be described by using one or the other of the Hardware Description Language (HDL) Verilog or VHDL.   Figure 3 illustrates the QPSK modulation and shows its constellation diagram. Here each symbol is associated with a phase of the signal. By going counter clockwise the symbols "11", "01", "00" and "10" are found at angles of 3 /4, 5 /4 (−3 /4), and 7 /4 (− /4 ) respectively. The constellation diagram of the QPSK can be drawn from Equation 4, where fc is the frequency of the carrier: From Equation 4 we derive the following expressions of ( , ): (0,1) = − cos( ) + sin( ) (1,0) = cos( ) − sin( ) (1,1) = cos( ) + sin ( ) The following rules to model the QPSK encoder are based on the IEEE Standard 802.16-2004: Where 1/√2 is normalization factor of the the modulated waveform. Equation 9 dictates that the four symbols are separated by /2, with the first symbol "11" located at the angle of /4. Thus, the QPSK modulator having four symbols offers a higher data transmission rate than the BPSK modulator. Now if we look at the reception level, ie at the QPSK and BPSK demodulators, we note that the signal after passing through the channels paired with transmission noises, the BPSK demodulator has only two decisions to make while the QPSK demodulator has four. This tells us that the BPSK modulation is more robust than QPSK modulation using only two phases makes signal reception easier for the demodulator circuit. These two modulation schemes are widely used in today's communication systems. Depending on the design objectives, compromises will be made between speed and robustness. Here, we propose a new architecture that meets these two criteria and more.

NEW RECONFIGURABLE QPSK, 8-PSK, AND 16-PSK ARCHITECTURE
Here, a new architecture to implement a reconfigurable PSK modulator is presented in Figure 4. The proposed design consumes very little power and occupies a negligible space in the FPGA. This design is reconfigurable in real time (1) manually using two switches or (2) by software via programming. Although the three modulation schemes QPSK, 8-PSK, and 16-PSK are present in the FPGA bitstream, only one scheme can be selected at a time. Note that the circuit reconfiguration is done without the need of regenerating the FPGA configuration bits; therefore without any interruption of service. This has never been done in the past. Moreover, the proposed algorithm can be used to generate PSK modulation types up to N-PSK. Having in mind that the more we add phases ie 32-PSK and so on the more the reception of data will be difficult at the receiver end. This feature of real-time reconfiguration is very effective in situations of very strong jamming. Like the frequency hopping technique which consists of changing frequencies to counter jammings, here the scheme of the PSK modulation will be the parameter to change to accomplish the same task. Accordingly, the three modulation schemes implemented can be preprogrammed to be used in turn creating a phase hopping as a means of protection in the presence of jamming attacks. For this type of Electronic Protection Measure (EPM) to be effective, the modulator and the demodulator must be well syntonized. That is, the demodulator must be preprogrammed with the same phase hopping sequences used in the modulator. The Pseudocode for the algorithm is given in Table 1 to generate the different associated phases for the desired modulation. The constellation decoder module (phase encoder) depending on the type of modulation selected is responsible for calculating the ROM read start address. The state machine in this architecture will read the ROM continuously until a new symbol is received from the serial to parallel converter module. The latter generates the symbols for the three types of modulator being QPSK, 8-PSK, and 16-PSK. For each symbol, a unique start address for reading in the ROM is assigned, thus for each new symbol received the read counter is initialized to the new start address value calculated. That said, these start addresses indicate the phases of the modulator that are generated. The ROM contains the waveform to be used by the encoder phase module to generate the different phases of the selected modulation scheme. We used the 3-wire SPI controller core from Digilent TM to program the generic modulator and to communicate the transmission data to the SPI interface of the DAC used. The DAC used is the Digilent PMODDA2 which is a 12-bit DAC with 1Million samples / sec. The phase encoder module is a key part of the proposed modulator. It controls the access to the ROM and decodes the signals at the output of the serial to parallel converter. With Sn,p being the constellation points on the constellation diagram we have: With m=1, 2… 2 p+3 and p=0, 1, 2 for QPSK, 8-PSK and 16-PSK respectively. Table 2 shows the pseudocode used in the process of generating the phases for the three types of modulation described above. This pseudocode can be extended to 32, 64-PSK and so on. As shown in Figure 4, we used a single ROM of size 256x12 to contain the sinusoidal signal that we will be used to modulate our data signal. Initially, the system is reset to address zero by default regardless of the selected modulation type, QPSK, 8-PSK, and 16-PSK. By selecting the "start mode", the modulator begins receiving the serial data signal and routes it to the serial to parallel converter. The serial to parallel converter is reconfigurable into 1 bit to 2-bit parallel converter, 1 bit to 3-bit parallel converter and finally into 1 bit to 4-bit converter to accommodate the QPSK, 8-PSK, and 16-PSK respectively. The converter will generate the symbols from the input serial signal. By selecting the type of modulation to be generated, the pseudocode for the HDL below is used to generate the phase differences.

ENCRYPTION KEY GENERATOR CIRCUIT
Random numbers are essential to ensure the security of telecommunications, whether they are used in cryptographic algorithms such as Diffie-Hellman and RSA, or in frequency hopping mechanisms to name a few. It is important that randomness be part of the seed of a security algorithm to avoid reverse engineering. However, RNGs are often made in software through an algorithm and True RNGs (TRNGs), RNGs made in hardware, are often costly. This section of this article shows how to build a low cost TRNG that can reach very high entropy. Many such circuits have been reviewed. However, we used the circuit described in [15] as a starting point to create our noise generating circuit. In [15], bipolar junction transistors (BJT) have been used as a source of noise. In the modified architecture we replaced the two BJTs upstream by two Zener diodes as shown in Figure 12. The advantage of using two identical noise sources is that they will likely have the same statistical distribution in terms of voltages. Therefore, we will end up with close to the same amount of 1's and 0's at the output of the comparator. In Figure 12, the noise generated by the two Zener diodes will be amplified before being routed to the comparator circuit. The result of this amplification is shown in Figure  13 (a). Figure 13 (b) shows the frequency domain representation of the circuit which only measures noise as expected. Therefore, the output of the comparator will be a mixture of the high frequency and low frequency components. In order for this output signal to be usable, the high frequency components that can be considered as glitches must be removed using a low-pass filter.
Before applying the low-pass filter, the digital output as depicted in Figure 14 looks noisy. Therefore, it is necessary to do some statistical analysis to ensure that the bits generated are indeed random. Using NIST SP-800-90B (Second draft), we implemented several functions using Matlab to conduct this statistical analysis. The goal is to determine whether or not the bits are Independent and Identically Distributed (IID). Twenty tests were made using the sampled bits. These include calculating the amount of rising and falling edge, covariance tests, periodicity tests, etc. The results of every test were then compared to 10,000 binary lists shuffled using the Fisher-Yates algorithm. Two counters were used to compare the results: C0 was incremented when the output of a test was greater for the shuffled list and C1 was incremented when the output of the test was the same for the shuffled list and the sampled list. NIST determines that a sample is non-IID if (C0 + C1) ≤ 5 or if C0 ≥ 9995 for any test. Since the results obtained were far from those values, we concluded that the bits were IID according to NIST's standard. Then, we calculated a min-entropy of 0.96 using the Most Common Value Estimate (section 6.3.1 of NIST's SP-800-90B).

CONCLUSION
In the time of conflicts fast and accurate exchanging or gathering of intelligence between allies over a secured channel is an asset. Digital modulations techniques are widely used in wireless communication. Accordingly, in this article, we have proposed and described a new reconfigurable PSK modulator. The circuit is realized on the Digilent Genesis 2 development board. It consumes only 303 mW of power. The experimental results for the three types of modulations implemented (QPSK, 8-PSK, and 16-PSK) agree with the simulation data. The synthesis and implementation phases were carried out with a clock of 200 MHz. This clock has been reduced to meet the conversion rate of the PMODDA2 DAC. However, the FMC port of the Genesis 2 development board allows interfacing with the Analog Device AD-FMCDAQ2-EBZ evaluation board. The ADC (AD9680) and DAC (AD9144) mounted on the the AD-FMCDAQ2-EBZ support input data rate of 1.25 GSPS and 2.8 GSPS respectively. Therefore, by using the AD-FMCDAQ2-EBZ in conjunction with the Genesis 2 development board we will no longer need to do a down conversion of the current clock frequency. In addition of proposing this new design, we have also explored some avenues to generate random encryption keys. We arrived at a circuit capable of generating random encryption keys. This circuit has demonstrated a min-entropy of 0.96. This result is very promising to ensure data security.