Design and Analysis of CMOS Low Noise Amplifier Circuit for 5-ghz Cascode and Folded Cascode in 180nm Technology

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.


INTRODUCTION
Due to rapid growth of wireless communication industry, the increasing demand upon wireless devices has motivated the development of CMOS radio frequency integrated circuits (RFICs). LNAs are used in various wireless applications like Wi-Fi, Bluetooth, wireless voice, data and video. Many of this applications operate in 2 to 5GHz. The Wi-Fi of IEEE 802.11ac protocol is used for 5GHz band.

RF Design
Many decades of work on RF and Microwave theory and two decades of research on RF IC's. Design and implementation of RF circuit and transceiver remains challenging. RF circuits and transceiver must deal with numerous trade-offs. The demand for high performance, lower cost and greater functionality continues to present new challenges. RF design hexagon, consists of six parameters related with each other to some extent. RF design of parameters is represented in a Figure 1. Low Noise amplifiers are based on Radio frequency communication receivers and the specifications we can estimate overall noise performance of the RF receivers. The RF signal received at the antenna is weak, using an amplifier with high gain and noise performance is needed to amplify the signal before it can be fed to other parts of the receiver. Such amplifier is referred to as a Low Noise Amplifier (LNA).

Low Noise Amplifier
The Low noise amplifiers are one of the basic building blocks of any communication systems. The demand of high performance wireless front-end system is increasing nowadays. The main aim on low power mobile devices with low cost. Low noise amplifier is the first stage of an RF receiver contributes to the noise of the entire receiver. The main function of the LNA is to amplify the weak signals from the antenna.
The first stage of the receiver contributes mainly to the overall Noise Figure (NF) of the receiver. The main performance parameters of LNAs are Gain, Noise Figure (NF), linearity and stability. The forward gain of LNA is defined by the S-parameters. The NF is defined as the ratio of signal to Noise Ratio (SNR) at the input to the SNR at the output. Third-order intercept point (IP3) and 1dB compression point (P1dB) are the measures of linearity. LNA is stable it satisfies the condition stability Factor, K>1. But always there will be a trade-offs in power, linearity, gain frequency and noise and of the design parameters.
The design and simulation of basic Common Source (CS) stage with inductive degeneration, using Cascode stage and Folded Cascode stage. The designed cascode stage is having a NF which is very less compared to the LNAs. The cascode LNA can used in an environment with weak signal strength as it is having a very good gain. Section II deals with the basic concepts of different methods of LNA topologies. Section III having the design considerations. In section IV reported about simulation results and in section V reported the conclusion.

BASIC LOW NOISE AMPLIFIER TOPOLOGIES
LNA topologies using Common Source and Common Drain with Cascode and Folded Cascode.

Common Source (CS) with Inductive Degeneration
The inductive degenerated topology is narrow-band since the input matching circuit consisting of the source inductors and the gate to source capacitance, Cgs, resonates at a single frequency. The inductively degenerated LNA is the dominating topology for narrow-band systems due to its advantages such as low Noise Figure

Cascode
The most commonly used topology for LNA design is the cascode amplifier with inductive source degeneration. The cascode topology has higher gain, due to the increase in the output impedance. The cascode transistor suppresses the Miller capacitance of the reverse isolation. The suppression of the parasitic capacitance of the input transistor is suppressed which improves the high frequency operation of the amplifier.

Folded Cascode
In a cascode stage, relatively large bias voltage is required due to the stacking design of the Common Source and Common gate transistors. So for Low voltage applications, a folded cascode topology is used. Due to absence of stacking gain stages, the operating voltage of the folded cascode LNA can be reduced by one transistor overdrive.

DESIGNING
Using various applications in the 5GHz have varying design constraints. For the gain and Noise Figure should be extremely 40dB and 1dB respectively. The equations from equation (1) to equation (9) are used to design the source inductor LS, gate inductor Lg, drain inductor Ld and width of the input device W.

W=
( 1 ) Where gm is the trans-conductance of the device, Cgs is the gate source capacitance and RS is the source resistance which is equal to 50Ω in equation (6) and in equation (7) is the unity gain frequency of the MOS transistor. ωo is the centre frequency which is chosen to be 5GHz. In equation (1) COX is the oxide capacitance and Lmin is the minimum channel length which is 0.18µm in this design.

Cascode-lna
The Cascode LNA consists of three NMOS transistors are placed, transistor M1 is common source and M2 is common gate are connected to the inductive degeneration of LS, Ld, Lg and connected to LC tank. S-parameters of two ports are connected to the input and output of LNA. Cascode LNA is used further reduce the power consumption and improve the NF and Gain. The aspect ratio of the input device of width and length of transistor M1 and M2 and is 140µm/180nm and M3 is 28µm/180nm. Where Lg is 7nH, Ls is 1.72nH, Ld is 0.25nH. Capacitance Co and C1 is 10nH and C2 is 500fF. Resistance Rref is 2KΩ, Rbias is 3KΩ and R2 is 300Ω. The cascode LNA of Noise Figure (

Folded Cascode LNA
The folded cascode topology is designed to further improve the NF. In folded cascode LNA common source is NMOS is M1 transistor and common gate is PMOS is M2 transistor having the same aspect ratio. The circuit design using RC network is added in parallel with the inductor, Ld is 1.5nH, Lg is 5.7nH, Ls is 0.25nH, Lo is 6nH, capacitance Co and C1 is 10nF, C2 is 500fF, Port1 is 50Ω and Port2 is 500Ω. Transistors M1 is 140µm/180nm and M2 is 560µm/180nm. Resistance Ro is 300Ω.