An Optimal Design of CMOS Two Stage Comparator Circuit Using Swarm Intelligence Technique

ABSTRACT


INTRODUCTION
Analog integrated circuit (IC) design is one of challenging task in the growth of modern electronics system.The design of digital circuit is completely automated, and the analog functions are converted into digital value wherever possible.For last few decades, the electronics system design seemed that everything could be digital.However, the real world signals are analog in nature; these signals are communicated through analog circuits [1].For digital signal processing applications, it is necessary to interface the analog circuit to the system [2].In recent times, the analog circuit design regaining attention by researchers in the area of system on chip (SoC).The basic concept of SoC is to integrate both analog and digital circuit in a single chip.One of the main challenging tasks in designing SoC is to minimize analog circuit design time.For mixed signal system design, the absence of analog automated synthesis tool to increase the design cycle time.
Deterministic approach for analog circuit design needs good starting point, which can be assigned by analog designer [3][4][5][6].The accuracy of this method is depends on the dc point and the knowledge of analog designer.Then this method is interface with spice engine to enhance the design parameters.However, the deterministic approaches are not suitable for complex circuits [7].
Heuristic based optimization approaches can be used to model the analog circuit design problems.The most popular heuristic methods are local search [8], tabu search [9], and simulated annealing [10].These techniques were applied to the analog circuit design.These mathematical approaches implemented to form a model with different types of design variables and constraints.However these methods do not guarantee the optimal solution.Meta-heuristics algorithms were proposed to overcome the main issues of heuristic based optimization approaches.These algorithms are inspired from the nature and mainly they mimic the animal hunting behavior towards the food source.Some meta-heuristics approaches used for analog circuit design are particle swarm optimization [11], harmony search algorithm [12] and ant colony optimization [13].These techniques try to provide the optimal solution to the problem.The swarm intelligence techniques are mostly suitable for complex optimization problem [14][15][16].They have better ability to find the global optimal solution in reasonable time.The main motivation of this work is to optimize the transistor size and bias current value to meet the design specification of the CMOS comparator circuit.The simulation-based optimization technique is proposed to optimize the circuit design parameters.
In compared with other method the swarm intelligence based method provide the batter results.
The reaming part of this paper is organized as follows: Section 2 describes the comparator circuit structure and design specification.The third section presents the mathematical representation and the operations of salp swarm optimization.The fourth section describes the simulation results and discussion.Finally, the fifth section is the conclusion of work.

DESIGN SPECIFICATION AND OBJECTIVE FUNCTION FORMULATION
An optimal design of CMOS comparator has large number of design parameters.The special kind of design procedure required to handle the design variables.The design specifications for the comparator are dc gain, slew rate and power dissipation etc.For comparator design, input bias current, the transistor length and width are considered as the design variables.The relationship between these variables used to implement the design process of circuit.In order to obtain the optimal value of MOS transistor sizes and bias current value, the objective function is developed from the design specifications of the circuits [17].The objective function of proposed comparator is to minimize the total area of the chip.The circuit structure and configurations of the comparator circuit is shown in Figure 1.The design steps involved in the comparator circuit are as follows [18]: Find the range of 2. [] Find out the first stage voltage gain from overall gain Find out the current values following through M1, M2, M3 and M4 Find the value of biasing resistor (Rb), where The cost function of FPA is the given by (i.e.The total chip area of an operational amplifier) 1 () Where, N represents the number of transistors, Wi and Li are the width and length of transistors.

PROPOSED FLOWER POLLINATION ALGORITHM (FPA) FOR CMOS TWO STAGE COMPARATOR CIRCUIT OPTIMIZATION
Flower pollination algorithm is a population based meta-heuristics optimization algorithm, which mimics the flower pollination process of flowering plants and the basic structure of FPA is presented in [19].This algorithm is simple in nature and it has only two search operators namely, the global search operator and the local search operator.These two operators normally used to iteratively update the candidate solution.The mathematical representation of global search operator is expressed as, The FPA more likely uses the local search operator in order to solve optimization problem.This can be achieved by the probability coefficient (p) which is 0.8 for the local search operator and 0.2 for the global search operator.The Nelder-Mead is a local optimization technique used to improve the local search exploitation of FPA.The steps of proposed NMFPA are as follows: Step 1: Control parameter setting: the population size N, the switch probability p, maximum number of iteration and the parameters for the simplex method.
Step 2: Evaluate the N candidate solutions and find the best solution from that.
Step 3: Based on switch probability, generate a new solution using the local search operator or the global search operator.The new solutions are better than current solution then update the best solution.
Step 4: Select the n+1 best solution and form an initial simplex using Nelder-Mead method.Then execute m times and replace the previous selected n+1 solution.Now update the current best solution.
Step 5: Continue iterations form step 3 until the end condition satisfied.The main aim of this paper is to find the length and width of the transistor by utilizing the FPA.The input specification and its range are shown in Table 1

SIMULATION RESULT
This section describe the simulation result of FPA based CMOS comparator circuit design.The proposed hybrid optimization algorithm is constructed using MATLAB for the design of CMOS comparator.The design parameters and design constraints are considered as the input variable for optimization algorithm.The constant circuit design variables are taken from model parameter called GPDK 180nm technology.The main objective is aimed to minimize the total chip size of CMOS comparator circuit.The result obtained from the flower pollination algorithm based comparator design is compared with existing methods like Differential Evolution (DE) and Harmony Search (HS) algorithm [20].The input variables and their values are given in Table 1, in order to define the input range of an optimization problem.The comparator cost function is aimed to minimize the chip area less than 300 µm 2 .The simulation results show that the least chip area of 36.77µm 2 .An optimal transistor dimension values of the CMOS comparator are given in Table 2. To evaluate the efficiency of the proposed optimization technique is compared withther techniques called differential evolution and harmony search shown in Table 3 Figure 2 show the efficiency of proposed algorithm in terms of power dissipation.The simulation results show that the proposed optimization technique is most suitable for simple analog circuit design.

CONCLUSION
A new swarm intelligent technique for determining the transistor sizes, input bias current and other parameters of CMOS comparator is presented.Flower pollination algorithm (FPA) has shown its exploration and exploitation capability in finding the optimal design parameters in multidimensional search space.At the same time the proposed technique reduces the chip area, power dissipation and increases the DC gain of CMOS comparator.Simulation result demonstrates that the proposed algorithm successfully met the circuit design specification.The simulation results show that the FPA optimization method is efficient method for the design of simple analog circuits.

Figure 1 .
Figure 1.CMOS two stage comparator circuit in order to satisfy the positive ICMR.
satisfy the negative ICMR.

Figure 2 .
Figure 2. Power dissipation of two stage comparator circuit indicate two randomly selected solutions, and  represents a random number in [0, 1].
An Optimal Design of CMOS Two Stage Comparator Circuit Using Swarm… (Sasikumar)

Table 1 .
. Design Parameters, Technology and Constant values of Two-Stage Operational Amplifier

Table 3 .
Design Specifications Result of the CMOS Two Stage Comparator