Secured smart ATM transaction

The objective of this paper is to reduce the service tax during mobile transactions. To improve the security and to make the process easy and less time consuming this process is rendered with the help of GSM (Global System for Mobile communication), finger print sensors, PIC16F877A microcontroller and aadhaar number.


INTRODUCTION
Secured smart ATM transaction is newly innovated process from the conventional ATM transaction method. Card and pin number is used as an accessing key for money transaction in the ordinary ATM. But in SECURED SMART ATM TRANSACTION both card and the pin is eliminated instead of that Fingerprint authentication and GSM signal control is used. During normal money transaction process the sender who sends the money should transact the amount of money from his account to receivers account. Then receiver need to withdraw the cash from the ATM. But in Smart ATM Transaction sender need not required to transact money to receiver instead of that the sender can just provide an account accessing permission to withdraw limited amount of money from his/her account directly. By this, the processing steps of money transaction is reduced to half and also nearly 50% of service tax can be reduced which is highly useful for the large organization to distribute the salary to their numerous employees. Since the adhaar number and fingerprint of every user is scanned initially the cyber crime can greatly avoided. To improve the security, less cost consuming and less time consuming, we have innovated the SECURED SMART ATM TRANSACTION process.

PIC MICROCONTROLLER BLOCK DIAGRAM
Circumstances that we find ourselves in today in the field of microcontrollers had their beginnings in the development of technology of integrated circuits. This development has made it possible to store hundreds of thousands of transistors into one chip. That was a prerequisite for production of microprocessors, and the first computers were made by adding external peripherals such as memory, input-output lines, timers and other. Further increasing of the volume of the package resulted in creation of integrated circuits. These integrated circuits contained both processor and peripherals. That is how the first chip containing a microcomputer, or what would later be known as a microcontroller came about. Memory is part of the microcontroller whose function is to store data. For a certain input we get the contents of a certain addressed memory location and that's all. Two new concepts are brought to us: addressing and memory location.

Timers
The Timer0 module timer/counter has the following features: a. 8-bit timer/counter b. Readable and writable c. 8-bit software programmable prescaler d. Internal or external clock select e. Interrupt on overflow from FFh to 00h f.
Edge select for external clock Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. The prescales is mutually exclusively shared between the Timer0 module and the watchdog timer. The prescaler is not readable or writable.

Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP.

Pre-scalar
A pre-scalar assignment for the Timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. The PSA and PS2:PS0 bits. (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1, x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.

Timer1 Module
The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).Timer1 can operate in one of two modes 1) As a timer, 2) As a counter. The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Block diagram of the TIMER0/WDT Pre-scalar as shown in Figure 2. Timer1 module as shown in Figure 3.

MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE
The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: a. Serial Peripheral Interface (SPI) b. Inter-Integrated Circuit (I2C)

SPI Mode
The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: Additionally, a fourth pin may be used when in a slave mode of operation: Slave Select (SS). To enable the serial port, MSSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON registers, and then set bit SSPEN. Figure shows the block diagram of the MSSP module when in SPI mode. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed. That is: a. SDI is automatically controlled by the SPI module b. SDO must have TRISC<5> cleared c. SCK (Master mode) must have TRISC<3> cleared d. SCK (Slave mode) must have TRISC<3> set e. SS must have TRISA<5> set

Master Mode
The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave is to broadcast data by the software protocol. In master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI module is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>).

Slave Mode
In slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the interrupt flag bit SSPIF (PIR1<3>) is set. While in slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in sleep mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from sleep.

MSSP I2C Operation
The MSSP module in I2C mode fully implements all master and slave functions (including general call support) and provides interrupts-on-start and stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the SCL pin, which is the clock, and the SDA pin, which is the data. The SDA and SCL pins are automatically configured when the I2C mode is enabled. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>). The SSPCON register allows control of the I2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I2C modes to be selected: a. I2C Slave mode (7-bit address) b. I2C Slave mode (10-bit address) c. I2C Master mode, clock = OSC/4 (SSPADD +1) The SSPSTAT register gives the status of the data transfer. SSPBUF is the register to which the transfer data is written to or read from. In receive operations; the SSPBUF and SSPSR create a doubled buffered receiver. This allows reception of the next byte to begin before reading the last byte of received data. When the complete byte is received, it is transferred to the SSPBUF register and flag bit SSPIF is set. standard. The GSM standard is the most widely accepted standard and is implemented globally. The GSM is a circuit-switched system that divides each 200 kHz channel into eight 25 kHz time-slots. GSM operates in the 900 MHz and 1.8GHz bands in Europe and the 1.9GHz and 850MHz bands in the US. The GSM is owns a market share of more than 70 percent of the world's digital cellular subscribers. The GSM makes use of narrowband Time Division Multiple Access (TDMA) technique for transmitting signals. The GSM was developed using digital technology. It has an ability to carry 64 kbps to 120 Mbps of data rates. Presently GSM support more than one billion mobile subscribers in more than 210 countries throughout of the world. The GSM provides basic to advanced voice and data services including Roaming service. Roaming is the ability to use your GSM phone number in another GSM network.
A GSM digitizes and compresses data, then sends it down through a channel with two other streams of user data, each in its own time slot. It operates at either the 900 MHz or 1,800 MHz frequency band. Why GSM?
The GSM study group aimed to provide the followings through the GSM: Improved spectrum efficiency.

GSM Network
The MS and the BSS communicate across the Um interface, also known as the air interface or radio link. The BSS communicates with the Network Service Switching center across the A interface.

GSM Network Areas
In a GSM network, the following areas are defined

Cell
Cell is the basic service area: one BTS covers one cell. Each cell is given a Cell Global Identity (CGI), a number that uniquely identifies the cell.

Location Area
A group of cells form a Location Area. This is the area that is paged when a subscriber gets an incoming call. Each Location Area is assigned a Location Area Identity (LAI). Each Location Area is served by one or more BSCs.

MSC/VLR Service Area
The area covered by one MSC is called the MSC/VLR service area.

PLMN
The area covered by one network operator is called PLMN. A PLMN can contain one or more MSCs. Specifications for different Personal Communication Services (PCS) systems vary among the different PCS networks. The GSM specification is listed below with important characteristics.

Modulation
Modulation is a form of change process where we change the input information into a suitable format for the transmission medium. We also changed the information by demodulating the signal at the receiving end. The GSM uses Gaussian Minimum Shift Keying (GMSK) modulation method.

Location Area Identity (LAI)
Each LA of an PLMN has its own identifier. The Location Area Identifier (LAI) is also structured hierarchically and internationally unique as follows: Country Code (CC) 3 decimal places. Mobile Network Code (MNC): 2 decimal places. Location Area Code (LAC): maximum 5 decimal places or, maximum twice 8 bits coded in hexadecimal (LAC < FFFF).

Temporary Mobile Subscriber Identity (TMSI)
The VLR, which is responsible for the current location of a subscriber, can assign a temporary mobile subscriber identity (TMSI) which has only local significance in the area handled by the VLR. It is stored on the network side only in the VLR and is not passed to the HLR. Together with the current location area, TMSI allows a subscriber to be identified uniquely and it can consist of upto 4x8 bits.

Local Mobile Subscriber Identity (LMSI)
The VLR can assign an additional searching key to each mobile station within its area to accelerate database access. This unique key is called the Local Mobile Subscriber Identity (LMSI). The LMSI is assigned when the mobile station registers with the VLR and is also sent to the HLR. An LIMSI consists of four octets (4x8 bits).

Cell Identifier (CI)
Within an LA, the individual cells are uniquely identified with a cell identifier (CI), maximum 2 x 8 bits. Together with the global cell identity (LAI+CI) calls are thus also internationally defined in a unique way. The operation of the GSM system can be understood by studying the sequence of events that takes place when a call is initiated from the Mobile Station.

Call from Mobile Phone to PSTN:
When a mobile subscriber makes a call to a PSTN telephone subscriber, the following sequence of events takes place: a. The MSC/VLR receives the message of a call request. b. The MSC/VLR checks if the mobile station is authorized to access the network. If so, the mobile station is activated. If the mobile station is not authorized, service will be denied. c. MSC/VLR analyzes the number and initiates a call setup with the PSTN.

FINGER PRINT SENSOR
R305 Fingerprint Module is a serial fingerprint scanner which can be directly connected to the PC's com port. R305 Fingerprint Sensor can easily be connected to any controller via MAX232 IC. This Fingerprint scanner is capable of storing and comparing the fingerprint and accordingly giving the desired output. Fingerprint processing includes two parts: fingerprint enrollment and fingerprint matching (the matching can be 1:1 or 1: N). When enrolling, user needs to enter the finger two times. The system will process the two time finger images, generate a template of the finger based on processing results and store the template. When matching, user enters the finger through optical sensor and system will generate a template of the finger and compare it with templates of the finger library. For 1:1 matching, system will compare the live finger with specific template designated in the Module; for 1: N matching, or searching, system will search the whole finger library for the matching finger. In both circumstances, system will return the matching result, success or failure. a.  The analysis of fingerprints for matching purposes generally requires the comparison of several features of the print pattern. These include patterns, which are aggregate characteristics of ridges, and minutia points, which are unique features found within the patterns. It is also necessary to know the structure and properties of human skin in order to successfully employ some of the imaging technologies. Figure 9 shows salary details. Figure 10 shows hardware prototype. Figure 11 shows hardware output. 6. EMBEDDED CODING #include<pic.h> #include<string.h> #include"fingerprint.c" #include"gsm_driver_new.c" bank1 struct db{ unsigned char code [5]; unsigned char ad_no [5]; unsigned char f_id; }ac_holders[]={"1234","3232",0, "4321","4545",1, "5678","2345",2, "8765","5214",3}; bank1 unsigned char i,msg_code [5],msg_adno [5];