DESIGN AND SOFTWARE CHARACTERIZATION OF FINFET BASED FULL ADDERS

Adder is the most important arithmetic block that is used in all processors. Most of the logical circuits till today were designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET’s). In order to reduce chip area, leakage power and to increase switching speed, MOSFET’s were continuously scaled down. Further scaling below 45nm, MOSFET’s suffers from Short Channel Effects (SCE’s) which leads to degraded performance of the device. Here the Performance of 28T and 16T MOSFET based 1-bit full adder cell is characterized and compared with FinFET based 28T and 16T 1-bit full adders at various technology nodes using HSPICE software. Results show that FinFET based full adder design gives better performance in terms of speed, power and reliability compared to MOSFET based full adder designs. Hence FinFET are promising candidates and better replacement for MOSFET.


INTRODUCTION
Today there is a huge demand for portable applications such as laptops, iPhones etc. with limited amount of power availability, requiring minimum area and high switching speed circuitry [1]. Therefore, circuits which provide low power consumption and high switching speed becomes the major candidates for design of microprocessor and other subsystems [2]. Addition is a basic arithmetic operation and is used in most of the VLSI subsystems like application specific DSP architectures and microprocessors [9]. Therefore 1-bit Full Adder cell is the most important and basic block of arithmetic logic unit in digital systems.
In low power VLSI systems, Metal Oxide Semiconductor field effect Transistors (MOSFET's) are the basic transistors used in most of the digital circuits. Continuous scaling of MOSFET's has resulted in better performance of the device parameters such size, delay and power. Further scaling of MOSFETs below 45nm node technology leads to short channel effects (SCE's), which modifies the device characteristics. The major SCE's includes • Drain Induced Barrier Lowering.
To avoid these effects as well as to improve the switching speed ad to reduce the power requirements, MOSFET's were replaced by FINFET's in design circuitry [5] [6]. FINFET's are multiple gate devices. These multiple gates provide better control over the channel and hence reduce the short channel effects [6].
FINFET based adder in general shows an average of 94% drop in delay, 97% decrease in power dissipation over the conventional MOSFETs [7] [8].

FINFET TECHNOLOGY
FINFET known as Fin Field Effect Transistors non-planar or 3D transistor used to design modern processor. The main characteristics of FINFET is that it has a conducting channel wrapped by a thin silicon "fin" and hence the name FINFET. The thickness of the fin determines the effective channel length of the device. This wrap around gate structure provides better electrical control over the channel and this helps in reducing the leakage current and overcoming other short channel effects. This fin allows multiple gates to operate on single transistor. The multiple gates of FINFET extend Moore's Law which allows the semiconductor manufacturers to create microprocessor subsystem and memory modules that provides faster performances, less energy consumption and reduction in space complexity. The Fig.1 shows a FinFET structure. It has four terminals and it consists of source, drain and channel wrapped by multiple gates. Here we consider two gates FinFET structure namely front gate and back gate. FinFET can substitute in place of MOSFET by merely shorting the front and back gates together during device fabrication and allow FinFET work as single gate device.

1-BIT FULL ADDER CELL
The operation of 1-bit full adder cell includes three inputs A, B, Cin using which outputs sum and carry are calculated.
In this paper, a 1-bit full adder is implemented using both CMOS and FINFET technology. The full adder circuitry has been designed using different logic styles: • Conventional CMOS logic style.
• Complementary pass transistor logic and transmission gates logic.

MOSFET BASED FULL ADDER
The device parameters considered are based on predictive Technology Model (PTM) for developing a spice model and then simulating using HSPICE tool. The parameters are considered with respect to PTM as shown in the Table.2.  Fig.3 shows HSPICE user interface and integration, the netlist written for a particular circuit model is characterized via the Hspice user interface and the software is powerfully integrated to find the errors and produce the output results in accurate manner.

28T CONVENTIONAL CMOS FULL ADDER
This CMOS full adder consists of both PMOS and NMOS in the form of pull-up and pull-down network. The Fig.4 shows the schematic diagram of 28T conventional CMOS full adder cell.   Table.3. Same procedure is applied to all the node technologies evaluated using MOSFET and FinFET devices.   Table.3, it is clear that performance of MOSFET based full adder in terms of the power and delay values are obtained and it can be concluded that there is an increase in the power and delay values of MOSFET based Full Adder at 45nm node and below due to short channel effect faced by MOSFET devices.

16T MOSFET FULL ADDER
In order to reduce the number of transistors and to obtain optimum results, 16T full adder is designed and simulated using complementary pass transistors and transmission gates. The simulation is done in HSPICE tool. The Fig.7 shows the design of 16T MOSFET full adder cell.

FINFET BASED FULL ADDER
To overcome the scaling issue faced by MOSFET, full adder cell is designed using FINFET. The FinFET allows further scaling up to 14nm.

28T FINFET FULL ADDER
This full adder cell consists of both nFET and pFET to replace the complementary CMOS logic. The Fig.10 gives the schematic diagram of 28T FinFET full adder cell. The output waveforms of 28T full adder cell is as shown in Fig.11 and Fig.12.   Fig.11. Output waveform at 22nm

16T FINFET FULL ADDER
Similar to Fig.13 with 28T FinFET full adder cell, a schematic diagram of 16T FinFET based full adder cell can be drawn and characterized at 22nm and 14nm technology nodes as observed in following waveforms. The output waveforms of 16T full adder cell are as shown in Fig.13 and Fig.14.   Fig.13. Output waveform at 22nm

RESULTS AND DISCUSSIONS
The spice models of MOSFET based full adders are created for 28T and 16T at 90nm and 45nm and are simulated using HSPICE. The simulation waveforms are viewed using Avanwaves. The comparison of the results between 28T and 16T MOSFET based full adder cell is as shown in Table.8. From the comparisons made, it is analysed that (1) as number of transistors decreases, the power dissipation has decreased. (2) Scaling of MOSFET from 90nm to 45nm has led to increase in power dissipation. Hence further scaling down of MOSFET leads to degraded output and increase in leakage power.
The spice models based on PTM files are referred from BSIM-IMG for characterization of device and FinFET based full adders are built for 28T and 16T at 22nm and 14nm and are simulated using HSPICE. The comparison of the results between 28T and 16T FinFET based full adder cell at 22nm and 14nm nodes is as shown in Table.10.  From the comparisons of FinFET based full adder cell, we can analyse that FinFET has overcome the scaling issues of MOSFET as illustrated above at 22nm and 14nm.

CONCLUSIONS
The MOSFET and FinFET based full adder cell for 28T and 16T at different nodes are characterized using software mainly in terms of Power dissipation and delay. The obtained results for the FinFET full adder spice models used here shows a promising solution for MOSFETs scaling issues. The power dissipation in 28T FinFET based adder at 14nm is reduced to 32nW from 62nW at 22nm adder, similarly delay get reduced from 25ps to 13.9ps when node size is reduced from 22nm to 14nm node. Likewise, the results for the power and delays values for sum and carry operation are for 16T FinFET based full adders. And from the result table 6.3 and 6.4 it can be concluded that FinFET based full adder cell is reliable at lower technology nodes and the tolerant capacity is better at the nanometer regime. The power dissipation of the FinFET based device has decreased significantly at lower technology nodes. The speeds of the adder circuits are increased terms of the sum and carry delay operation. Thus FinFET based circuits are promising candidates for the future Digital systems.