Filtering and acquisition of serial data frames using xilinx system generator

ABSTRACT


INTRODUCTION
Over the past decade, R&D in sounding-type vectors and UAVs (Unmanned Aerial Vehicles) has enjoyed exponential growth in several disciplines: aeronautical systems, applied mechanics, on-board electronics, ground stations, real-time signal processing, etc. In this work, we will focus on ground-based signal processing methods to acquire PCM signals and distribute telemetric information to multiple monitoring clients [1,2]. Both unmanned aerial systems and sounding rockets require a ground station for the acquisition of telemetric signals and real time data processing whether for the control and monitoring of the mission or for the evaluation of the different scientific experiments installed on the platform [3]. The design of an acquisition system in a ground station is a complex task since it involves receiving data and sending it to the processing systems so that everything operates in real time. At the same time, on-board electronic systems are increasingly faster and easily adaptable to the requirements of the experiment. As a consequence, the data acquisition system changes constantly with every redesign of the platform. The aim of this work is to obtain a low-cost data acquisition system that allows the reception of high-speed PCM frames to decommute all of the channels with the physical magnitudes within the PCM frames [4]. The module developed draws on the progress of different methods for the synchronization of frame headers and data decommuting in the ground acquisition system, which will perform the information processing task in real time [5]. In particular, this PCM module was built to be used in atmospheric sounding vector evaluations by the Institute of Scientific and Technical Research for Defense of Argentina (CITEDEF). Some of the first bit-synchronizers systems was based on the generation of spectral line components by nonlinear filtering of the received bit stream, and extracting the line by a digital phase-locked loop (PLL) and data detection was realized by a digital matched filter (DMF) [6]. The implementation of these modules evolved over time with the need of speed from the utilization of TTL gates, then using microcontrollers, CPLDs and currently using a combination of Analog-Digital converters (ADC) [7] and FPGA devices to perform signal processing and data analysis applied for i.e. to complex navigation algorithms [8]. The motivation of this work was to exclude the ADCs to be able to use only low-cost FPGAs and to perform an analysis of the procurement behavior and associates by building arrays of data to images. The PCM signal input is still analog and enter to a digital-input of FPGA. This model converts directly the noisy analog signal to a Digital PCM (DPCM), perform a bit-synchronization and send the data to a PC through an USB connection [9,10]. On the other hand, the cost factor of trademark products was analyzed. All these are licencedsoftware, and are very expensive, and very difficult to adapt to scientific designs and developments where changes are permanent. This module developed is very low cost.

DESIGN
In order to achieve PCM signal regeneration, it is necessary to filter and observe the permanent regime state of the signal. The level (zero or one) at the midpoint of each bit is maintained despite the noise. Figure 1 shows the difference between the original transmitted signal and the received signal (note that the latter is band-limited, so the abrupt flanks no longer exist). The complete model ( Figure 2) shows two instances of the acquisition system: first, the filtering model (where you enter an ideal PCM frame with noise added) and second, the acquisition model (in charge of the synchronization).

DEVELOPMENT
The model with System Generator [11] provides a high level tool for the development of high performance systems using Xilinx devices with FPGA technology, and thus defines and characterizes logic circuits to fulfill a specific function. The main difference between any HDL and the rest of the programming languages is that the description languages are synthesized, not compiled or executed like any other program. This is due to the fact that programming languages are defined as procedures. Instead, the hardware description is based on the definition of behaviors according to the inputs and the desired processing concurrently [12]. During the synthesis, the interconnection of the available resources in the FPGA is defined so they behave in the way described. It is part of the work of the development tools to carry out the necessary optimization to take less resources or for the block to operate at higher frequencies. The System Generator automatically translates the block development of a Simulink [13] model into HDL by optimizing FPGA timing and area requirements, and also generates the final binary file [14]. The implementation in hardware was performed on the 3PX1 development kit manufactured by Emtech [15], with a Spartan-6 FPGA (XC6SLX25 [16]). This board meets the basic needs to initiate the development and prototyping of specific system applications with FPGA technology. The board also includes a flash memory where to store the firmware, push-buttons to use as inputs and LEDs to use as status indicators. It was mounted on an open cabinet made of acrylic to give greater rigidity to the board, also to be able to unify it as a single module with BNC connectors for connection and disconnection without compromising the FPGA device. Three connectors were placed on the front panel, two with the PCM Transmitter outputs (data and clock) and a third connector with the input to the acquiring system, Figure 3. The hardware design for the FPGA was performed using MATLAB [17] in conjunction with the System Generator, a tool provided by Xilinx to work in that environment. The MATLAB-Code was used to implement the MATLAB language directly on an FPGA, eliminating the need to program under VHDL or Verilog.

PCM filtering
To generate a realistic scenario, we add Additive White Gaussian noise (AWGN) to an ideal PCM signal. Thermal noise in an ideal resistor is approximately white, meaning that the power spectral density is nearly constant throughout the frequency spectrum (however see the section below on extremely high frequencies). When limited to a finite bandwidth, thermal noise has a nearly Gaussian amplitude distribution [18]. This design supports critical conditions where SNR could exceed -3dB (50% of the signal level). To achieve this, we perform a specific configuration of the "Noise generator" block and perform the noise measurement using the (1).
The SNR measurement model can be seen in Figure 4 and the results give a value of approximately 0.6 (-2.2dB), ie the SNR in this case is set to be -2.2dB (60% of the signal level), whereby the condition is completely secured ( Figure 5). This mentioned model to perform a SNR measurement has the particularity of doing it in real time, which is advantageous to test different simulation scenarios with different types of frames and times. This PCM filter sub-system implements a CIC filter (Cascaded Integrator-Comb). Implementations of CIC filters have structures that use only adders, subtracters, and delay elements. These structures make CIC filters appealing for their hardware-efficient implementations of multirate filtering [19]. In System Generator, the CIC filter block has a single input port and a single output port, xn and yn, M is the differential delay. In the decimator configuration, the sampling rate is reduced by a factor of R, sub-sampling the output of the last stage of the integrator [20]. As can be seen in Figure 6, the implemented model is a 10 step CIC filter that, despite consuming many resources and a large area of the FPGA, ensures a good filtering that meets the high level of requirement in the design. On the other hand, we must ensure that the width of each bit is kept equal to the output of the filter compared to its original ideal, so we adapt a filter 25:1, which generates 68-bit data at the end of the CIC filter [21]. These last data are compared to a constant to generate a digital pulse at the output of the subsystem. It was determined, by multiple tests and simulations, that the appropriate value of the constant is set to 5.1019 (gives a large value due to successive multiplications per input sample). Figure 7 shows Results of PCM data filtering. First channel: PCM Data w/noise, Second channel: CIC Output, Third channel: Filtering output. Figure 8 shows how the filtering is done correctly in a PCM data signal.

PCM acquisition
In order to process the PCM incoming data, it is important to first determine the start and end of each packet. Since from the point of view of the entry there is no distinction, the data entry is continuous and asynchronous. The development challenge is to be able to detect the beginning of each package, a pattern recognition or sync word detection, to regenerate the data synchronously for further processing.

Clock-Sync
The algorithm developed for the re-synchronization block is based on the rising edge detection of PCM data input. This sub-system ( Figure 9) performs a first PCM clock re-generation continuously and synchronizes automatically when a rising edge is detected in the incoming signal.

ReSync
The ReSync subsystem performs a pattern recognition of the sync-word to lock the incoming signal and re-synchronize it with the clock. To achieve this, two tandem blocks are used. The first one has a finite state machine and a shift register, to find the sync-word bit by bit (performs a bit-sync). The second generates additional signals to other blocks. The results of the simulation can be seen in Figure 10. In the last channel, we can see the incoming PCM data signal in the subsystem, and when the first rising edge is detected, the clock is re-synched, and a valid frame flag is activated, indicating a possible true PCM frame. From that moment, an algorithm starts to recognize the sync-word configurated (performed by a block which is called lock). Figure 10 shows how after 16 bits, the output is true indicating that the sub-system found a valid syncword. In this case, the sync-word is 1110101110010000 (EB9016). Several frequency measurements were performed with an analyzer. The PCM data (output of the PCM simulator) have 99.9998 kHz with a standard deviation of 1.1248 MHz, with 125 samples per second in a total of 10 seconds of duration. A second frequency stability measurement was performed with the PCM filtering and acquisition in full operation, and the results of the PCM clock regenerated are 9.9998 kHz with a standard deviation of 1.5216 MHz ( Figure 11). In conclusion, the error added by the model is practically null.  Figure 11. Results of regenerated PCM clock stability

Store
Frame storage in the system is essential for a protocol conversion or pre-processing algorithms. In this case, the acquisition system converts the incoming PCM data and sends it synchronized using the UART protocol, through to USB physical connection [22]. This sub-system combines M-Code block (MATLAB script code) taking the incoming flow of bits and the flag indicating a valid frame, and generates one byte for each channel of the frame. These bytes are stored in a distributed memory FIFO to decrease the resources and area of the FPGA, especially for low-cost devices where hardware resources are more limited without compromising the operation frequency. The operation of the Store sub-system is shown in Figure 12 and it can be observed how the sub-system takes the valid byte at the beginning of the frame, taking into account that the sync word is EB90 in hexadecimals.

Send
The Send subsystem collects the data stored in the Store block and serializes them with an 8N1 UART protocol (i.e. 1 word start bit, 8 data bits and one stop bit). Figure 13 shows a simulation result of the converted PCM frame.

IMPLEMENTATION AND RESULTS
By connecting the PCM simulator (a known frame used as a pattern) to the acquiring system, we can receive the data captured in a computer through an usb-serial port. The data will be dumped into a vector called serialdata. To perform the proposed analysis, we will convert serialdata into a matrix, where each column represents a complete frame (from the sync word to the end of the frame) and the column number is the received frame number. A sector of the acquired matrix (serialdata) can be seen in Table 1, where it shows the first 28 bytes (from frame 412 to frame 521); in particular, in the byte 7 of the frame 416 an error occurs. Figure 14 shows the matrix in an HSV color chart by treating it like an image. The matrix will be cropped to keep only the payload by deleting the first 4 bytes and the last byte, called serialdatamatrix. A new matrix of constants is generated representing the ideal matrix (as if there were no errors) called datamatrix. The two matrices are subtracted to a new matrix called dif (2). The resulting image is shown in Figure 15.
In total, 2102 errors were detected from a total of 1375232 bytes captured (21488 PCM frames at 5ms per frame with a length of 64 bytes each). Subtracting the first 4 bytes and the last (5 bytes in total), we have a total of 21488 frames of 59 bytes in payload, resulting in a total of 1267792 bytes. If we calculate the percentage of bytes with error vs. the total payload bytes, it gives an efficiency of 99.83%. The maximum error introduced by the acquiring system is 0.165%, assuming that the error occurs in the complete byte, i.e. the 8 bits are erroneous. This value is due to the fact that the acquiring system is re-engaged by each received frame. Other systems synchronize only once with the first valid sync-word. Therefore, if an error occurs in the medium of the acquisition of a frame, when it detects the sync-word of the next frame, it is re-accommodated. This shows that while the system introduces a small error in the telemetry chain, it is minimal and self-correcting, thus proving trustworthy for mission-critical applications. Figure 16 Shows the errors in PCM acquisition First: Number of errors accumulated in time, second: Residuals.

CONCLUSION
In total, 230 frames were found with errors, and a maximum of 5 errors per frame. If an entire frame discard policy is applied in case we found only one error, in total it would be 1.07% of discarded frames. Another important analysis is to corroborate the amount of erroneous data as a function of time by performing a fitting of number of frames received vs. number of errors accumulated in time. The errors fit in a linear equation. In other words, the system is constant-time efficient.
For the implementation of the PCM acquisition model, the base software and the FPGA device were used. The results of the final implementation, i.e. once the final hardware routing was generated after the synthesis. Also, we can highlight that it occupies a very little area of the hardware. Therefore, this system is compatible with low-cost FPGA devices, where the area and resources are very limited.

ACKNOWLEDGMENTS
The present R&D work was carried out under the supervision of my PhD thesis director, PhD. Mario Lavorato, and the Head of the Applied Electronics Department, Eng Edgardo Comas, to whom I would like to express my deepest appreciation for making this study possible. In addition, I would also like to thank all the personnel working at the Laboratory of Digital Techniques in CITEDEF, who permanently collaborate in the development of software and hardware for this type of applications. Finally, I am very grateful to the CITEDEF authorities for the logistics support and to MINDEF (Argentine Department of Defense), which provides financial support to this type of programs and projects.