A Power Efficient Self Biased OTA Design Based on gm/ID Methodology with Considering Load Variation, Temperature Variation and Power Supply Variation

Received Apr 1, 2018 Revised Jun 20, 2018 Accepted Jul 7, 2018 The present work addresses the design of power efficient fully self biased OTA using a design methodology based on the gm/ID transistor characteristics. This analog module was analyzed, designed and prototyped in TSMS 0.35μm CMOS technology. Simulation results are presented, in order to validate the methodology. The OTA has Gain of 41.35 dB and 3db bandwidth of 138.73 kHz and the UGB of 12.40MHz with the current consumption of 65.50 μA. The circuit does not have need of any DC external biasing circuit, only need to apply VDD (3.3 V). Here self biasing has been introduced with power consumption of 216.15μW. The results have been taken with load variations, temperature variations, and power supply variations. This circuit used in real time high frequency applications as in RF communication.


INTRODUCTION
The development of ultra-scaled VLSI technologies, coupled with the demand for more signal processing integrated in a single chip, has resulted in a tremendous potential for design of analog circuits. Most VLSI systems require analog sub-systems such as amplifiers, comparators, filters, oscillators, digital-to-analog and analog-to-digital converters. Most often the target technology process imposes design tradeoffs, some of them taken based on designer's experience with the target technology to achieve a successful analog design. More critical in deep sub-micron CMOS mixed-signal ICs are the specifications of analog circuits that are sensitive to the random variations of the size and technology parameters. This work focuses on the analysis, design and implementation of a low power OTA using the / design method [1]. In this method, we consider the relationship between the / ratio and the normalized drain current /(W/L) as a fundamental design information to explore in the design space. In several analog blocks [2,3], including the Gm-C filter [4], were designed using this methodology. Preliminary simulation results shows that a conventional design approach (using first-order Spice level 1 transistor models) achieves a similar performance with similar area, hence incurring in much larger power dissipation than that obtained in the / design method. The process parameters were obtained through the library files of TSMC 0.35μm CMOS technology [5]- [10].

SELF BAISED OTA ARCHITECTURE
Self biased circuit is the circuit in which there is no need of any external biasing circuit at any stage; means we made circuit in such a way that it take the biasing voltage from any node of the present circuit. Self Biased Circuit is able to bias its output to an equivalent bandgap voltage without using any external voltage reference or extra pin. A self-biased architecture which has an operating point independent of the process technology and environmental variations hence rendering a more robust design [11], [12]. The selfbiased architecture also gives a constant ratio of the bandwidth to reference frequency and a constant damping factor. These ensure the stability of a OTA while at the same time keeping the phase noise low across the entire reference frequency range [13]. Fixed bias circuits get their bias voltages from independently designed reference voltage sources (or even something as simple as a voltage divider). Often in that case the bias may be left for the end-user to give some control over the operation point of the circuit. Self biased circuits get their bias voltages from the circuit itself often in the form of a negative feedback. This is very useful when a circuit is extremely sensitive to bias points and it becomes impractical to provide external biases that are correct to very high accuracies. This can happen in high gain amplifiers with very high impedance output nodes such as a common source amplifier with an active load [14], [15]. The operation of the circuit depends on the bias of the active load. It would therefore be desirable to sacrifice some of this gain by providing a negative feedback from the output to the gate of the active load. This way you would not have to bias the circuit yourself but will lose some of the gain of the circuit as a price. This is one of the trade off of analog circuits [17]- [19]. The circuit for self baised OTA is shown in Figure 1. The biasing for the input transistors MN1 and MN2 are provided by the drain terminal (node P) of MP1, there is no need of external biasing circuit is required for operating this OTA. Here, there is only need to apply AC input. Designing is in such a manner that the voltage at point P is 1.6534volt. Here MP1 is using also as a current source for providing current to MN3 and which is mirroring in MN4.

DESIGN IMPLEMENTATION OF OTA
Considering the OTA design specifications and the chosen OTA architecture, the transconductor was designed using the / methodology [20]- [25]. For each transistor, the / factor is chosen, and then the normalized current /(W/L) is determined for each transistor from the / vs. /(W/L) curve for the target technology. Then, with the drain current value found, the W/L of each transistor can be obtained.
The complete design procedure is demonstrated as follows: a. Considering SR specification, the bias current is determined: Ibias ≥ SR.CL, Ibias →=75μA; b. From the transconductance gain requirement of 35 dB and ID1=12.5μA, the / ratio of the NMOS differential pair (MN1-MN2) can be determined:    Table 1 after iterations. Here after iterations the circuit have made circuit in such a way that the DC voltage of output node of the first stage is on 1.65 V. This will provide a DC input to the next OTA stage. The fully self biased OTA was then implemented according to the topology showed in Figure 3. All transconductors operate with one common bias generating circuit, which improves the matching between the OTA's stage.

LAYOUT 4.1. Analog Layout
When low-level or high-precision circuitry is being designed, a lot of care is usually given to the details of the circuit schematic and how the signal runs are routed. In layouts for digital circuits, the speed and the area are the two most important issues. In contrast, the layout for analog circuits, everything should be considered simultaneously [26]. In addition to the speed and the area, other equally critical considerations should be taken into account. In analog layout more care has to be given as the circuit performance changes drastically due to noise, mismatches, crosstalk and shielding required to protect critical nodes from being disturbed [27]. Without proper layout, the mismatches and the coupled noise would be quite large and would significantly degrade the performance of the amplifiers [28].

Layout of OTA
Due to huge aspect ratio, some transistors are divided into multiple fingers [29]. Figure 5 shows all the transistors with fingerings. Aspect ratio of MN1 and MN2 is 100/1.4. Since 100=2  50, so a single transistor is divided in to 2 fingers with width of 50µm. There is no need to make fingers of other transistors of OTA, because sizes of these transistors are very small.

SIMULATION AND RESULTS
In this Chapter the schematic of the circuit has been simulated for various parameters. All values have been measured at load capacitance of 3pF. Prepared circuit of OTA is simulated at Tanner, T-SPICE tool at 0.35µ technology. This OTA is to be powered from a 3.3 volts power supply and with a power dissipation of 216μW. The current sources/sinks required for biasing are used from output stage. Based on the OTA, input stage is fully self biased, an OTA has been designed. The simulations include AC response, Transient analysis, DC Response. The responses have been checked for temperature variation, Load capacitance variation and power supply variation. There is no need to give any DC at the input because this circuit is fully self biased that's why there is no need to make any biasing circuit.

AC Analysis:
On applying AC of 10 mv and DC of 0 V at input terminal of designed filter. (Here VDD is 3.3V with respect to ground). Figure 6 shows AC Analysis for OTA. The netlist and the simulated AC results for the gain (magnitude in dB) with respect to frequency(Hz) has been plotted by using TSMC 0.35µm on T-SPICE tool (Tanner), is given in Figure 7. From Figure 7 plotted waveforms, the following parameters have been obtained as in Table 2.

Transient Analysis
For observing the transient response of the filter the test setup of Figure 8 must be used. In this setup sinusoidal signals are applied to the two inputs and the effective value of input signal is the difference of the voltage at the two terminals. No DC potential is applied along with the sinusoidal signal because the circuit is fully self biased.  Figure 9. On applying the input voltage peak to peak of 1mv, output voltage peak to peak of 220mv has been obtained. Here max voltage swing is 1.72V and min voltage swing is 1.50V. The simulated transient results for the magnitude in volt with respect to time (sec) have been plotted in Figure 9. On applying the input voltage peak to peak of 1mv, slew rate of 9.992 µs has been obtained.

DC Analysis
The main response of this circuit is the DC response. As no biasing voltage at the input is used, single voltage source i.e. power supply (VDD) provides the necessary DC voltage at the input.
Here the voltage of every node is almost equal to 1.65 volt.

a) DC Value of VOUT1
The voltage of node VOUT1 is plotted in Figure 10, when the value of VDD is 3.3 volt, then on this value, the voltage at node VOUT1 is 1.61 Volt.

b) DC Value of VOUT2
The voltage of node VOUT2 is plotted in Figure 11, when the value of VDD is 3.3 volt, then on this value the voltage at node VOUT2 is 1.61 Volt. Figure 10. Voltage of Node VOUT1 Figure 11. Voltage of node VOUT2

Load Variations:
On applying different values of load capacitance differences in all the achieved parameters have been obtained. The achieved parameters have been plotted in the following figures for three different (2.5 PF, 3 PF, 3.5 PF) values. From Figures 12, 13 and 14 plotted waveforms, the following parameters have been obtained as in Table 3.

AC Analysis
AC analysis has been done first for all three temperatures. From Figure 15, plotted waveforms, the following parameters have been obtained as in Table 4. According to Table 5 this has to be seen that as temperature is increasing, each parameter is improving. Gain and Bandwidth is maximum at 300C.

DC Analysis
The DC analysis has been done for all three temperatures and the values for all three nodes have been plotted. According to the Figure 16 and Figure 17 this has to be seen that there is no effect on the DC voltages of all nodes. So this has to be said that the circuit is resistant for common mode signal and can be operated on different temperatures.

Power Supply Variations
The effect of the variation in power supply has been plotted. From Figure 18, plotted waveforms, the following parameters have been obtained as in Table 5. According to the Table 5 this has to be seen that the overall performance of the circuit is increasing for lesser value of power supply.

CONCLUSIONS
Self biasing is the area of biasing, which reduces the area requirement of the circuit. As the technology is scaled down it is more important for a filter to work at any CM level. Here in this thesis work, fully self biased OTA using a design methodology based on the / transistor characteristics is designed and simulated with the schematic of the circuit.
The OTA has Gain of 41.35 dB and 3db bandwidth of 138.73 kHz and the UGB of 12.40MHz with the current consumption of 65.50 μA. The circuit does not have need of any DC external biasing circuit, only need to apply VDD (3.3 V). Here self biasing has been introduced with power consumption of 216.15μW.
The operation of the input stage under different supply voltages and temperature are simulated and analyzed. Simulation result for temperature variation, power supply variations and load variations shows that the circuit can be used for wide range of temperature, power supply and load variation. The main feature of the circuit is the self biasing with low current consumption of 65.5μW.