On-chip AMBA Bus Based Efficient Bridge between High Performance and Low Peripheral Devices

ABSTRACT


INTRODUCTION
The AMBA™ on-chip interconnect system is an established open specification that details a strategy on the interconnection and management of functional blocks that makes up a System-on-Chip (SoC). It is a high-speed, high-bandwidth bus that supports multi-master bus management to maximize system performance.
On March 8, 2010, ARM announced availability of the AMBA 4.0 specifications. As the de facto standard SoC bus, AMBA bus is widely used in the high-performance SoC designs. The AMBA specification defines an on-chip communication standard for designing high-performance embedded microcontrollers. The AMBA 4.0 specification defines five buses/interfaces [ AXI, the next generation of AMBA interface defined in the AMBA 4.0 specification, is targeted at high performance, high clock frequency system designs and includes features which make it very suitable for high speed sub-micrometre interconnect. Typically the AXI2.0 protocol [2] has five channels for dedicated operation which can initiated the data transfer and control.

Character of AXI Bus
To correctly grasp the complexity of the design challenge facing an engineer of an AMBA 3 AXI protocol-based design, [3] we must first understand the technical features of the AMBA 4 AXI 2.0 protocol itself. [4] The key feature is that AXI separates the data channels into five independent data channels (write data channel, write address channel, write response channel, read data channel, read address channel). Each channel transfers data in only one direction, and there is no requirement for a fixed relationship [5] between the various channels. This is important because it enables the insertion of a register slice in any channel. It is also possible to use register slices at almost any point within a given interconnection. It is very advantageous to use a direct, fast connection between a processor and high-performance memory, but to use simple register slices to isolate a longer path to less performance critical peripherals.
Besides the above feature, AMBA 4 AXI 2.0 protocol supports many advanced accessing manners, such as exclusive access and unaligned transfer. The AXI protocol enables out-of-order transaction completion and the issuing of multiple outstanding addresses. These features enable the implementation of a high performance. Interconnection, [6], [7] maximizing data throughput and system efficiency. Furthermore, the protocol also defines low power interface to meet the need of reducing power in MPSOC system by issuing how to entry and exit low power state.

AXI Bus Architecture
At the point of data transaction, AXI protocol defines five independent channels as shown in Figure  1. Both write and read address channels have their own addresses to transfer, as well as the control information that describes the nature of the data to be transferred. AXI bus uses a write data channel to transfer data from master to slave and a read data channel to transfer data from slave to master. In write transaction, there is an additional write response channel to indicate the state of the transaction.
The AXI bus consists of five independent channels, [3] each of which contains a set of information signals and uses a two-way VALID and READY handshake mechanism. The VALID signal from source indicates that the data or control information is available, and the READY signal from destination indicates that it is ready to accept data. When both VALID and READY signals go to high, data is transferred. The AXI protocol is burst based transaction, so both read data channel and write data channel use LAST signal to show when the transfer of the final data item within a transaction takes place. At the point of master and slave devices, it can be divided into master, slave and the interconnection architecture which connects masters and slaves together. A typical system consists of a number of master and slave devices connected together via some form of interconnection. And we are free to choose the interconnection according to the need of system

APB
The AMBA APB is for low-power peripherals. AMBA APB [6] is optimized for minimal power consumption and reduced interface complexity to support peripheral functions. APB can be used in conjunction with either version of the system bus.  This block is responsible for the communication interface between AXI master and APB slave. [8] once the control pin is stored in the FIFO according to CLK frequency of AXI master then FIFO will assert its FIFO full control according to the response of FIFO full, master stop its operation and then control is transferred to APB salve, and same way if read operation is done by APB slave then FIFO empty will be high and read operation will be stop. Asynchronous FIFO will take care of the high speed and low peripheral device interaction with different CLK write and read operation.
AXI Master Interface:-It is initiator of the operation between it take care of the operation by using its five channel and each channel have an asynchronous FIFO interface, so that protocol mismatch is resolved.
APB slave: It take care of the interface between master and device. If device is interacting to processor it has to interact with salve first, and slave will response according to analysis of control signal.it follows following state machine for its control  Figure 6 shows simulation results of APB slave. Figure 7 shows RTL view of APB slave. Figure 8 shows RTL diagram of APB slave. Figure 9 shows RTL view of AXI APB Bridge. Figure 10 shows simulation results of AXI APB bridge