Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm

ABSTRACT


INTRODUCTION
In computers, considerable amount of processing time is spent by the CPU on implementing arithmetic operations, particularly multiplication operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multipliers [1].
Thus multiplication time becomes one of the dominant factor in determining the instruction cycle time of a processor. The need for high speed processing is increasing as computer and signal processing applications are expanding and the development of fast multiplier circuit has been a subject of interest over decades [2]. In the binary multiplier, multiplication is implemented generally with a sequence of addition, and shift operations. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. This optimization includes the circuit style and topology, the architecture for implementing the circuits. Employing this technique in the computation algorithms will reduce the complexity, execution time, power. The method can also be used to compute NxN multiplication, by reducing the NxN structure into an efficient 8x8 multiplier structures [3].

RESEARCH METHOD (URDHVA TIRYAKBHYAM)
The proposed multiplier algorithm is based on Urdhva Tiryakbhyam Sutra of ancient Indian Vedic Mathematics. Urdhva Tiryakbhyam Sutra is a general multiplication formula applicable to all cases of IJRES ISSN: 2089-4864  Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise… (G.Subramanya Nayak) 37 multiplication. It literally means "Vertically and crosswise". It is based on a concept of generating of all partial products in parallel (at once) and the final result is obtained by adding these partial products concurrently as shown in Figure 1. It should be clearly noted that carry may be a multi-bit number [4]. This algorithm traditionally used for the multiplication of two numbers in the decimal number system. In this work, the same logic is used for the binary number system to make the proposed algorithm compatible with the digital hardware.

Figure 1. Vertically and crosswise multiplication
To illustrate the multiplication algorithm, we have considered the multiplication of two binary numbers a3a2a1a0 and b3b2b1b0. As the result of this multiplication would be more than 4 bits, we express it as r7r6r5r4r3r2r1r0. The circuit is designed making use of the proposed method and carry look ahead adder concept. The circuit makes use of 72 logic gates and the design is implemented using Circuit Maker software. The expressions used to calculate final product is shown in Figure 2 and the circuit diagram is shown in Figure 3 respectively. In the Vedic Multiplier each multiplicand bit is multiplied with all the bits of the multiplier, starting from MSB. The products are arranged (crosswise) as shown in Figure 4.
Then the bits are added vertically, the carry generated from the lower bit addition is added to the next stage sum, by using the carry look ahead method. Note that the carry generated may be multi bit. Thus sum obtained by the crosswise and vertical multiplication and addition of bits of the two numbers. The example of decimal number multiplication is illustrated in the Figure 4. The general sequential multiplier makes use of shifter and adder. Thus to generate the result of 4x4 multiplication requires 4 shift operations to generate the 16 product terms plus addition of these partial product terms. The flowchart of the sequential multiplier is given in Figure 5. Figure 6 and Figure 7 illustrates the binary multiplication by sequential and Vedic method respectively. Absence of the shift operation in the Vedic multiplier not only increases the speed of the operation but also helps in reducing the area and power required for the design [5], [6].

CONCLUSION
This hardware design of Vedic can be looked as similar to the array multiplier. All the partial products are calculated in parallel and the delay associated is mainly the time taken by the carry to propagate through the adders plus the partial products generation from the logic gates. As the number of bits increases for 8x8 bits, 16x16 bits the timing delay is greatly reduced for Vedic multiplier as compared to other multipliers. Vedic multiplier has the greatest advantage as compared to other multipliers over gate delays and regularity of structures.