Simulation and Real Time Implementation of Various PWM Strategies for 3 Φ Multilevel Inverter Using FPGA

ABSTRACT


INTRODUCTION
Multilevel inverters offer a number of advantages when compared to its conventional two-level inverter counterpart. The stepped approximation of the sinusoidal output using higher levels reduces the harmonic distortion of the output and the stresses across the semiconductor devices and also allows higher voltage/current and power ratings. Rajesh Gupta et al [1] proposed switching characterization of cascaded multilevel inverter controlled systems. Palanivel and Dash [2] evaluated THD and output voltage of three phase cascaded MLI using multicarrier PWM techniques. Rajesh Gupta et al [3] developed multiband hysteresis modulation and switching characterization for sliding-mode-controlled cascaded MLI. Ghoreishy et al [4] proposed methods for reducing common-mode voltage and power dissipation in cascaded multilevel inverters with flexible DC sources. Malinowski et al [5] carried out a detailed survey on cascaded multilevel inverters. Zhong et al [6] discussed fundamental frequency switching strategies of a seven level hybrid cascaded H-bridge multilevel inverter. Teodorescu et al [7] developed a multilevel inverter using cascaded industrial voltage source inverter. Corzine et al [8] proposed control for cascaded multilevel inverter. Deepa  [9] undertook harmonic analysis of a modified cascaded multilevel inverter. Zambra et al [10] Compared neutral point clamped, symmetrical and hybrid asymmetrical multilevel inverters. Youheihinago and Hirotaka Koizumi [11] proposed a single phase multilevel inverter using switched series/parallel DC voltage sources. Risnidar et al [12] discusses the influence of harmonics in laboratory due to Nonlinear Loads. Mohammad Jamil in [13] made a comparison on multilevel inverters with reduction of common mode voltage. Manjunatha and Anand [14] suggested a multilevel DC link inverter with reduced switches and batteries. Balamurugan et al [15] introduced a new bipolar hybrid carrier PWM strategies for symmetrical multi level inverter. Balamurugan et al [16] made a comparison between simulation and dSPACE based implementation of various PWM strategies for a new H-type FCMLI topology. This literature survey reveals few papers only on various PWM techniques and hence this work presents a novel approach for controlling the harmonics of output voltage of chosen MLI employing sinusoidal PWM switching strategies with triangular carriers. Simulations are performed using MATLAB-SIMULINK. Harmonics analysis and evaluation of performance measures for various modulation indices have been carried out and presented.

MULTILEVEL INVERTER
The multilevel inverters have drawn tremendous interest in the power industry. Multilevel inverters are also well suited for use in reactive power compensation. Power electronics technologies have also provided an important improvement of renewable energy applications. Many renewable energy applications will require high power inverters (>50 kW); for instance, a grid connected inverter. Therefore, multilevel inverters are suitable for this application because a multilevel inverter can possibly provide the high volt ampere ratings; multilevel inverters will significantly reduce the magnitude of harmonics and increases the output voltage and power without the use of step-up transformer. A cascaded multilevel inverter consists of a series of H-bridge inverter units connected to three phase R-L load. The general function of this multilevel inverter is to synthesize a desired voltage from several DC sources. The AC terminal voltages of each bridge are connected in series. Unlike the diode clamped or flying-capacitors inverter, the cascaded inverter does not require any voltage clamping diodes. This configuration is useful for constant frequency applications such as active front-end rectifiers, active power filters, and reactive power compensation. In this case, one of the very efficiently used control strategies is the space vector based control, which can be implemented using digital signal processor. Fig.1 shows the three phase cascaded multilevel inverter with induction motor load. The general function of this multilevel inverter is to produce a preferred voltage from several separate DC sources, which may be obtained from batteries, fuel cells or solar cells. Each DC source is connected to an Hbridge inverter. The operation of cascaded multilevel inverter is based on the separate DC sources. Each inverter level can generate three different voltage outputs, +V dc , 0 and -V dc using various combinations of four switches. The number of output phase voltage levels m in a cascaded inverter is defined by m=2s+1, where s is the number of separate DC sources. Using the example, turning on T a1 and T a4 yields +V dc output voltage, turning on T a2 and T a3 yields -V dc output voltage, turning off all switches yields no output. Fig. 1 show the power circuit of three phase cascaded multilevel inverter. The AC output voltage at other bridges can be obtained in the same manner. Controlling the conducting periods of switches of different inverter bridges can minimize the harmonic distortion of the output voltage. Several forms of renewable zero pollution energy resources including wind, solar, bio, geothermal can be used by cascaded multilevel inverter.

MULTICARRIER PWM METHODS
This work used the intersection of a sine wave reference signal with triangular carrier waves to generate firing pulses. There are five alternative strategies to implement this objective and Figure 2 shows a sample PWM generation logic.

Phase Disposition PWM Strategy
The rules for phase disposition method Figures (3 and 4) for a multilevel inverter are a. 4 carrier waveforms in phase are arranged. b. The converter is switched to + 2Vdc when the sine wave is greater than both upper carrier waveform. c. The converter is switched to + Vdc when the sine wave is greater than first upper carrier waveform. d. The converter is switched to zero when sine wave is lower than upper carrier but higher than the lower carrier. e. The converter is switched to -Vdc when the sine wave is less than first lower carrier waveform. f. The converter is switched to -2Vdc when the sine wave is less than both lower carrier waveforms.
The following formula is applicable to sub harmonic PWM strategy i.e PD, POD and APOD PWMs.

Phase Opposition and Disposition PWM Strategy
Four carrier waveforms are arranged so that all carrier waveforms above zero are in phase and they are 180 degrees out of phase with those below zero see Figures 5 and 6.

Alternative Phase Opposition and Disposition PWM strategy
Carriers are arranged in such a manner that each carrier is out of phase with its neighbor by 180 degrees see Figure 7 and 8.

Phase Shift PWM Strategy
The phase shift multicarrier PWM technique uses four carrier signals of the same amplitude and frequency which are shifted by 90 degrees to one another to generate the five level inverter output voltages see Figure 9 and 10. The gate signals for the cascaded inverter can be derived directly from the PWM signals (comparison of the carrier with the sinusoidal reference). There is a certain degree of freedom in the allocation of the carriers to the inverter switches. The amplitude modulation index m a =A m /(A c /2)

Hybrid PWM Strategy
The hybrid PWM strategy is the combination of phase disposition and phase shift strategy. Hybrid PWM strategy is illustrated see Figure 11

SIMULATION RESULTS
To verify the proposed schemes, a simulation model for a three phase five level cascaded H-bridge inverter is implemented using MATLAB as in Figure 2. Simulations are performed for different values of m a ranging from 0.5 to 0.9 and the corresponding %THD is measured using the FFT block and their values are shown in Table 1. Figures 13 -32 show the simulated output voltages of CMLI and their harmonic spectrum with different PWM strategies but for only one sample value of m a= 0.8 for R-L load. Figure 13 shows the five level output voltage generated by PDPWM strategy (m f =63 with f c =3.15KHz and f m =50Hz) and its FFT plot is shown in Figure 14. From Figure 14 it is observed that the PDPWM strategy produces significant 53 rd , 55 th , 59 th and 61 st harmonic energy. Figure 15 shows the five level output voltage generated by PDPWM strategy (m f =120 with f c =6KHz and f m =50Hz) and its FFT plot is shown in Figure 16. From Figure 16 it is observed that the PDPWM strategy produces significant 110 th , 112 th , 116 th and 118 th harmonic energy. Figure  17 shows the five level output voltage generated by PODPWM strategy (f c =3.15KHz) and its FFT plot is shown in Figure 18. From Figure 18 it is observed that the PODPWM strategy produces significant 56 th , 58 th and 62 nd harmonic energy. Figure 19 shows the five level output voltage generated by PODPWM strategy (f c =6KHz) and its FFT plot is shown in Figure 20. From Figure 20 it is observed that the PODPWM strategy produces significant 114 th , 116 th and 120 th harmonic energy. Figure 21 shows the five level output voltage generated by APODPWM strategy (f c =3.15KHz) and its FFT plot is shown in Figure 22. From Figure 22 it is observed that the APODPWM strategy produces significant 58 th , 60 th and 62 nd harmonic energy. Figure 23 shows the five level output voltage generated by APODPWM strategy (f c =6KHz) and its FFT plot is shown in Figure 24. From Figure 24 it is observed that the APODPWM strategy produces significant 116 th , 118 th and 120 th harmonic energy. Figure 25 shows the five level output voltage generated by HYBRIDPWM strategy (f c =3.15KHz) and its FFT plot is shown in Figure 26. From Figure 26 it is observed that the HYBRIDPWM strategy produces significant 53 rd , 55 th , 56 th , 58 th and 62 nd harmonic energy. Figure 27 shows the five level output voltage generated by HYBRIDPWM strategy (f c =6KHz) and its FFT plot is shown in  Figure 28 it is observed that the HYBRIDPWM strategy produces significant 113 th , 114 th , 116 th and 120 th harmonic energy. Figure 29 shows the five level output voltage generated by PSPWM strategy (f c =3.15KHz) and its FFT plot is shown in Figure 30. From Figure 30 it is observed that the PSPWM strategy does not produce significant harmonic energy. Figure 31 shows the five level output voltage generated by PSPWM strategy (f c =6KHz) and its FFT plot is shown in Figure 32. From Figure 32 it is observed that the PSPWM strategy does not produce significant harmonic energy. The following parameters were chosen for the simulation V dc= 20V, f c= 3.15KHz and 6KHz, R=100 ohms and L= 0.5 mH.

EXPERIMENTAL RESULTS
This section presents the results of experimental work carried out on chosen CMLI using SPARTAN 3E development board (Model No: VPTB-05) SPARTAN-3EXC3S100E FPGA. This kit provides a low cost, easy to use development and evaluation platform for Spartan -3E FPGA designs. Real time implementation of these strategies using FPGA requires less time for development. The Spartan-3E includes the following components and features, 100000 gates, 2160 logic cell equipment, Four 18 K-bit block RAMs (72 K bits), Four 18×18 pipelined hardware multipliers, two digital clock managers (DCMs), 32 Mbit Intel strata flash, 3 numbers of 20 pin header to interface VLSI based experimental modules, 8 input dip switches, 8 output LEDs, on board programmable oscillator (3 to 200 MHz), 16×2 alphanumeric LCD, RS232 UART, 4 channel 8 bit 12c based ADC and single channel DAC, PS/2 keyboard/mouse, prototype area for user applications, on board configuration flash PROM XCFOIS. The gate signal generation using different PWM strategies listed above is designed and developed using VLSI software. The result of the experimental study are shown in the form of the output voltage and FFT spectrum of chosen CMLI. Optocoupler circuit provides isolator between the control circuit and the power converter circuit. The optocoupler used is 6n137 which is an optically coupled gate that combines a GaAsp light emitting diode and an integrated high gain photo detector. An enable input allows the detector to be strobed, The output of the detector `IC is inversion of the applied input. The PWM signal from the FPGA are not capable of driving the MOSFETs. On order to strengthen the pulses a driver circuit is provided. The result of the experimental study are shown in the form of the oscillograms of PWM outputs and harmonic spectrum of chosen CMLI. Figs. 35-44 Show the experimental output voltage and corresponding harmonic spectrum of chosen CMLI obtained using SPARTAN-3E with PD, POD, APOD, PS and Hybrid PWM strategy respectively. The input voltage of each H-bridge is 20V. Figure 34 shows the entire hardware setup.

CONCLUSION
Three phase multilevel inverter fed R-L load is simulated using the blocks of Simulink in this work. The simulation results are compared for two different switching frequencies. It is observed that HYBRID and PSPWM methods provide output with relative low distortion for low and high f c respectively and PODPWM and PSPWM are found to perform better since they provide relatively higher fundamental RMS output voltage for R-L load with f c =6 and 3.15KHz respectively. If the switching frequencies are increased there is a slight decrease in the THD and slight increase in the Vrms. Table 1 Table 2 shows the Vrms values for various modulation indices. Table 3 shows the crest factor for both m a . Table 4 display the form factor for different modulation indices. Table 5 provides the distortion factor. The experimental results shows PSPWM provide output with low distortion and HYBRID provide output with high fundamental RMS voltage for f c =3.15KHz. The experimental results were obtained only for f c =3.15KHz.